VHDL 增量信号不能正常工作
VHDL Increment Signal doesn't work properly
我的 vhdl 代码有问题。我有一个信号，我想增加每个阶段。所以我写了这段代码：
--module.vhd
enter image description here
library ieee;
use ieee.std_logic_1164.all;
--use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
entity module is
port( CLK, RESET: in std_logic;
MODE: in std_logic_vector(1 downto 0);
Q: out std_logic_vector(3 downto 0));
end;
architecture arch of module is
--##INSERT YOUR CODE HERE
signal Q_INT : std_logic_vector(3 downto 0); --local signal
begin
process(RESET,CLK)
begin
if CLK = '1' and CLK'event then
if RESET ='1' then
Q <= (others => '0');
else
Q <= Q_INT;
case MODE is
when "00" => Q_INT<= Q_INT + "0001";
when "01" => Q_INT<= Q_INT +"0010";
when "10" => Q_INT<= Q_INT +"0011";
when "11" => Q_INT<= Q_INT +"0100";
when others => null;
end case;
Q <= Q_INT;
end if;
end if;
end process;
--if (MODE = "00") then
--Q_INT <= Q_INT + "0001";
--elsif (MODE = "01") then
--Q_INT <=Q_INT + "0010";
--elsif (MODE = "10") then
--Q_INT <=Q_INT + "0011";
--elsif (MODE = "11") then
--Q_INT <=Q_INT + "0100";
--end if;
--Q <= Q_INT;
--end process;
--##INSERT YOUR CODE HERE
end;
测试台看起来像这样：
library ieee;
use ieee.std_logic_1164.all;
entity TB_MODULE is
end TB_MODULE;
architecture TESTBENCH of TB_MODULE is
constant tbase: time:=10 ns;
constant tcheck: time:=1 ns;
signal TB_CLK: std_logic;
component MODULE
port( CLK, RESET: in std_logic;
MODE: in std_logic_vector(1 downto 0);
Q: out std_logic_vector(3 downto 0));
end component;
signal TB_RESET: std_logic;
signal TB_MODE: std_logic_vector(1 downto 0);
signal TB_Q: std_logic_vector(3 downto 0);
signal expTB_Q: std_logic_vector(3 downto 0);
begin
CLOCK: process
begin
TB_CLK <='1';
wait for tbase/2;
TB_CLK <='0';
wait for tbase/2;
end process CLOCK;
DUT: MODULE port map(TB_CLK, TB_RESET, TB_MODE, TB_Q);
STIMULI: process
begin
TB_RESET<='1','0' after 1*tbase, '0' after 2*tbase;
TB_MODE<="00", "00" after 1*tbase, "01" after 2*tbase, "10" after 3*tbase,
"11" after 4*tbase, "00" after 5*tbase;
expTB_q<=x"0", x"1" after 1*tbase, x"3" after 2*tbase, x"6" after 3*tbase,
x"A" after 4*tbase, x"B" after 5*tbase, x"C" after 6*tbase; --then incrementing
wait; -- end simulation
end process STIMULI;
--simmuli templates
--STIMULI: process
--begin
-- TB_RESET<='1','0' after 1*tbase, '0' after 2*tbase;
--
-- TB_A<='0', '0' after 1*tbase, '1' after 2*tbase, '0' after 3*tbase,
-- '0' after 4*tbase, '1' after 5*tbase;
-- TB_B<='0', '0' after 1*tbase, '0' after 2*tbase, '0' after 3*tbase,
-- '1' after 4*tbase, '1' after 5*tbase;
--
-- expTB_q<='0', '0' after 1*tbase, '0' after 2*tbase, '0' after 3*tbase,
-- '0' after 4*tbase, '1' after 5*tbase;
-- wait; -- end simulation
--end process STIMULI;
--STIMULI: process
--begin
--TB_A<=0', '0' after 1*tbase, '0' after 2*tbase, '0' after 3*tbase,
-- '0' after 4*tbase, '0' after 5*tbase, '0' after 6*tbase, '0' after 7*tbase,
-- '1' after 8*tbase, '1' after 9*tbase, '1' after 10*tbase, '1' after 11*tbase,
-- '1' after 12*tbase, '1' after 13*tbase, '1' after 14*tbase, '1' after 15*tbase;
--TB_B<='0', '0' after 1*tbase, '0' after 2*tbase, '0' after 3*tbase,
-- '1' after 4*tbase, '1' after 5*tbase, '1' after 6*tbase, '1' after 7*tbase,
-- '0' after 8*tbase, '0' after 9*tbase, '0' after 10*tbase, '0' after 11*tbase,
-- '1' after 12*tbase, '1' after 13*tbase, '1' after 14*tbase, '1' after 15*tbase;
--TB_C<='0', '0' after 1*tbase, '1' after 2*tbase, '1' after 3*tbase,
-- '0' after 4*tbase, '0' after 5*tbase, '1' after 6*tbase, '1' after 7*tbase,
-- '0' after 8*tbase, '0' after 9*tbase, '1' after 10*tbase, '1' after 11*tbase,
-- '0' after 12*tbase, '0' after 13*tbase, '1' after 14*tbase, '1' after 15*tbase;
--TB_D<='0', '1' after 1*tbase, '0' after 2*tbase, '1' after 3*tbase,
-- '0' after 4*tbase, '1' after 5*tbase, '0' after 6*tbase, '1' after 7*tbase,
-- '0' after 8*tbase, '1' after 9*tbase, '0' after 10*tbase, '1' after 11*tbase,
-- '0' after 12*tbase, '1' after 13*tbase, '0' after 14*tbase, '1' after 15*tbase;
--expTB_bus<="0000", "0001" after 1*tbase, "0010" after 2*tbase,
-- "0011" after 3*tbase, "0100" after 4*tbase, "0101" after 5*tbase,
-- "0110" after 6*tbase, "0111" after 7*tbase, "1000" after 8*tbase,
-- "1001" after 9*tbase, "1010" after 10*tbase, "1011" after 11*tbase,
-- "1100" after 12*tbase, "1101" after 13*tbase, "1110" after 14*tbase,
-- "1111" after 15*tbase;
--expTB_buxhex<=x"0", x"1" after 1*tbase, x"2" after 2*tbase, x"3" after 3*tbase,
-- x"4" after 4*tbase, x"5" after 5*tbase, x"6" after 6*tbase, x"7" after 7*tbase,
-- x"8" after 8*tbase, x"9" after 9*tbase, x"A" after 10*tbase, x"B" after 11*tbase,
-- x"C" after 12*tbase, x"D" after 13*tbase, x"E" after 14*tbase, x"F" after 15*tbase;
--end process STIMULI;
end TESTBENCH;
现在我的问题是我没有得到 Q_Int 的正确值。它始终是 'X'。 （但我想得到一个号码。感谢 enter image description here帮助
您的代码在语法上是正确的，并且会按要求的数量递增 Q_int。问题是 Q_int 被初始化为“UUUU”并且在重置时没有被赋值。当您向“UUUU”添加任何内容时，您会得到“UUUU”。
这里的答案是：
给出 Q_int 和初始值：
例如
signal Q_int : std_logic_vector(3 downto 0) := "0000";
或在重置发生时分配 Q_int 一个值
if RESET ='1' then
Q_int <= "0000";
--etc
第二种情况也将避免在重置 Q 时通过不重置 Q_int 创建的重置-> 时钟启用连接。
附带说明一下，您使用的是非标准 VHDL 库 std_logic_unsigned。建议您坚持使用标准 vhdl 库 numeric_std 并使用 unsigned 类型，或者对于 VHDL 2008，您可以使用 ieee.numeric_std_unsigned 包，它允许您使用 std_logic_vector作为数字无符号值。
signal Q_int : std_logic_vector(3 downto 0) := (others => "0");
你应该只初始化你的信号，你可以在顶层模块或测试台上自行完成。
我的 vhdl 代码有问题。我有一个信号，我想增加每个阶段。所以我写了这段代码：
--module.vhd enter image description here
library ieee;
use ieee.std_logic_1164.all;
--use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
entity module is
port( CLK, RESET: in std_logic;
MODE: in std_logic_vector(1 downto 0);
Q: out std_logic_vector(3 downto 0));
end;
architecture arch of module is
--##INSERT YOUR CODE HERE
signal Q_INT : std_logic_vector(3 downto 0); --local signal
begin
process(RESET,CLK)
begin
if CLK = '1' and CLK'event then
if RESET ='1' then
Q <= (others => '0');
else
Q <= Q_INT;
case MODE is
when "00" => Q_INT<= Q_INT + "0001";
when "01" => Q_INT<= Q_INT +"0010";
when "10" => Q_INT<= Q_INT +"0011";
when "11" => Q_INT<= Q_INT +"0100";
when others => null;
end case;
Q <= Q_INT;
end if;
end if;
end process;
--if (MODE = "00") then
--Q_INT <= Q_INT + "0001";
--elsif (MODE = "01") then
--Q_INT <=Q_INT + "0010";
--elsif (MODE = "10") then
--Q_INT <=Q_INT + "0011";
--elsif (MODE = "11") then
--Q_INT <=Q_INT + "0100";
--end if;
--Q <= Q_INT;
--end process;
--##INSERT YOUR CODE HERE
end;
测试台看起来像这样：
library ieee;
use ieee.std_logic_1164.all;
entity TB_MODULE is
end TB_MODULE;
architecture TESTBENCH of TB_MODULE is
constant tbase: time:=10 ns;
constant tcheck: time:=1 ns;
signal TB_CLK: std_logic;
component MODULE
port( CLK, RESET: in std_logic;
MODE: in std_logic_vector(1 downto 0);
Q: out std_logic_vector(3 downto 0));
end component;
signal TB_RESET: std_logic;
signal TB_MODE: std_logic_vector(1 downto 0);
signal TB_Q: std_logic_vector(3 downto 0);
signal expTB_Q: std_logic_vector(3 downto 0);
begin
CLOCK: process
begin
TB_CLK <='1';
wait for tbase/2;
TB_CLK <='0';
wait for tbase/2;
end process CLOCK;
DUT: MODULE port map(TB_CLK, TB_RESET, TB_MODE, TB_Q);
STIMULI: process
begin
TB_RESET<='1','0' after 1*tbase, '0' after 2*tbase;
TB_MODE<="00", "00" after 1*tbase, "01" after 2*tbase, "10" after 3*tbase,
"11" after 4*tbase, "00" after 5*tbase;
expTB_q<=x"0", x"1" after 1*tbase, x"3" after 2*tbase, x"6" after 3*tbase,
x"A" after 4*tbase, x"B" after 5*tbase, x"C" after 6*tbase; --then incrementing
wait; -- end simulation
end process STIMULI;
--simmuli templates
--STIMULI: process
--begin
-- TB_RESET<='1','0' after 1*tbase, '0' after 2*tbase;
--
-- TB_A<='0', '0' after 1*tbase, '1' after 2*tbase, '0' after 3*tbase,
-- '0' after 4*tbase, '1' after 5*tbase;
-- TB_B<='0', '0' after 1*tbase, '0' after 2*tbase, '0' after 3*tbase,
-- '1' after 4*tbase, '1' after 5*tbase;
--
-- expTB_q<='0', '0' after 1*tbase, '0' after 2*tbase, '0' after 3*tbase,
-- '0' after 4*tbase, '1' after 5*tbase;
-- wait; -- end simulation
--end process STIMULI;
--STIMULI: process
--begin
--TB_A<=0', '0' after 1*tbase, '0' after 2*tbase, '0' after 3*tbase,
-- '0' after 4*tbase, '0' after 5*tbase, '0' after 6*tbase, '0' after 7*tbase,
-- '1' after 8*tbase, '1' after 9*tbase, '1' after 10*tbase, '1' after 11*tbase,
-- '1' after 12*tbase, '1' after 13*tbase, '1' after 14*tbase, '1' after 15*tbase;
--TB_B<='0', '0' after 1*tbase, '0' after 2*tbase, '0' after 3*tbase,
-- '1' after 4*tbase, '1' after 5*tbase, '1' after 6*tbase, '1' after 7*tbase,
-- '0' after 8*tbase, '0' after 9*tbase, '0' after 10*tbase, '0' after 11*tbase,
-- '1' after 12*tbase, '1' after 13*tbase, '1' after 14*tbase, '1' after 15*tbase;
--TB_C<='0', '0' after 1*tbase, '1' after 2*tbase, '1' after 3*tbase,
-- '0' after 4*tbase, '0' after 5*tbase, '1' after 6*tbase, '1' after 7*tbase,
-- '0' after 8*tbase, '0' after 9*tbase, '1' after 10*tbase, '1' after 11*tbase,
-- '0' after 12*tbase, '0' after 13*tbase, '1' after 14*tbase, '1' after 15*tbase;
--TB_D<='0', '1' after 1*tbase, '0' after 2*tbase, '1' after 3*tbase,
-- '0' after 4*tbase, '1' after 5*tbase, '0' after 6*tbase, '1' after 7*tbase,
-- '0' after 8*tbase, '1' after 9*tbase, '0' after 10*tbase, '1' after 11*tbase,
-- '0' after 12*tbase, '1' after 13*tbase, '0' after 14*tbase, '1' after 15*tbase;
--expTB_bus<="0000", "0001" after 1*tbase, "0010" after 2*tbase,
-- "0011" after 3*tbase, "0100" after 4*tbase, "0101" after 5*tbase,
-- "0110" after 6*tbase, "0111" after 7*tbase, "1000" after 8*tbase,
-- "1001" after 9*tbase, "1010" after 10*tbase, "1011" after 11*tbase,
-- "1100" after 12*tbase, "1101" after 13*tbase, "1110" after 14*tbase,
-- "1111" after 15*tbase;
--expTB_buxhex<=x"0", x"1" after 1*tbase, x"2" after 2*tbase, x"3" after 3*tbase,
-- x"4" after 4*tbase, x"5" after 5*tbase, x"6" after 6*tbase, x"7" after 7*tbase,
-- x"8" after 8*tbase, x"9" after 9*tbase, x"A" after 10*tbase, x"B" after 11*tbase,
-- x"C" after 12*tbase, x"D" after 13*tbase, x"E" after 14*tbase, x"F" after 15*tbase;
--end process STIMULI;
end TESTBENCH;
现在我的问题是我没有得到 Q_Int 的正确值。它始终是 'X'。 （但我想得到一个号码。感谢 enter image description here帮助
您的代码在语法上是正确的，并且会按要求的数量递增 Q_int。问题是 Q_int 被初始化为“UUUU”并且在重置时没有被赋值。当您向“UUUU”添加任何内容时，您会得到“UUUU”。
这里的答案是： 给出 Q_int 和初始值： 例如
signal Q_int : std_logic_vector(3 downto 0) := "0000";
或在重置发生时分配 Q_int 一个值
if RESET ='1' then
Q_int <= "0000";
--etc
第二种情况也将避免在重置 Q 时通过不重置 Q_int 创建的重置-> 时钟启用连接。
附带说明一下，您使用的是非标准 VHDL 库 std_logic_unsigned。建议您坚持使用标准 vhdl 库 numeric_std 并使用 unsigned 类型，或者对于 VHDL 2008，您可以使用 ieee.numeric_std_unsigned 包，它允许您使用 std_logic_vector作为数字无符号值。
signal Q_int : std_logic_vector(3 downto 0) := (others => "0");
你应该只初始化你的信号，你可以在顶层模块或测试台上自行完成。