如何正确实例化模块并将寄存器传递给它

Question

[![模拟：模块似乎是运行但不是 passing/recieving 合适的信息？][1]][1]

我正在尝试熟悉 Xilinx iSim 实用程序。我很乐意模拟一个独立的模块。然而，当我开始引入和实例化多个模块时，我得到了意想不到的结果。下方模块 BCD_sevseg 似乎不接受任何输入，因为它的时钟根本不会循环，更不用说与顶部模块时钟

同步了

我不确定究竟如何构建测试平台，但我确信我对我要完成的工作的理解存在更根本的问题。然而，之前使用类似结构的尝试实现得非常好，我的 FPGA 按预期运行。

我已验证以适当的顺序传递了适当的值，并且在语法检查或模拟时我没有收到任何错误或警告。

我的顶级模块正在“实例化”（这个词正确吗）BCD_sevseg 模块如下

BCD_sevseg 应该接受 clk（可能是不好的做法），一个四位数，和 return 等效十进制数 [=16] 的 LED 状态的适当组合=]

很可能我在这里违反了很多“公认的做法”，但我现在真的只是想让测试台正常运行。

我相信这些是请求的模块。

测试台

`timescale 1ns / 1ps



module mod_10_II_sim;

    reg clk;
    
    reg clock;
    reg [3:0] bin_sevseg_value;

    wire led_a;
    wire led_b;
    wire led_c;
    wire led_d;
    wire led_e;
    wire led_f;
    wire led_g;
    
    
    wire a;
    wire b;
    wire c;
    wire d;
    wire e;
    wire f;
    wire g;

    
    BCD_sevseg inst_one(
        .clock(clock),
        .bin_sevseg_value(bin_sevseg_value),
        .a(a),
        .b(b),
        .c(c),
        .d(d),
        .e(e),
        .f(f),
        .g(g)
        );
    
    mod_10_top uut (
        .clk(clk), 
        .led_a(led_a), 
        .led_b(led_b), 
        .led_c(led_c), 
        .led_d(led_d), 
        .led_e(led_e), 
        .led_f(led_f), 
        .led_g(led_g)
    );
            

    initial begin

        clk = 0;
        clock = 0;
        bin_sevseg_value = 0;
        
        #100;
        
        

    end
    always #10 clk = ~clk;
endmodule

顶级模块

`timescale 1ns / 1ps

module BCD_sevseg( clock, bin_sevseg_value, a, b, c, d, e, f, g);

        input clock;
        input [3:0] bin_sevseg_value;
        
        output a;
        output b;
        output c;
        output d;
        output e;
        output f;
        output g;
        
        reg A = 1'b0;
        reg [0:0] B;
        reg [0:0] C;
        reg [0:0] D;
        reg [0:0] E;
        reg [0:0] F;
        reg [0:0] G;

        assign a = A;
        assign b = B;
        assign c = C;
        assign d = D;
        assign e = E;
        assign f = F;
        assign g = G;
        
        always @(posedge clock) begin
            
            case (bin_sevseg_value) 
                4'b0000: begin
                            A <= 1;
                            B <= 1;
                            C <= 1;         
                            D <= 1;
                            E <= 1;
                            F <= 1;
                            G <= 0;
                            end
                            
                4'b0001: begin
                            A <= 0;
                            B <= 1;
                            C <= 1;         
                            D <= 0;
                            E <= 0;
                            F <= 0;
                            G <= 0;
                            end
                        
                4'b0010: begin
                            A <= 1;
                            B <= 1;
                            C <= 0;         
                            D <= 1;
                            E <= 1;
                            F <= 0;
                            G <= 1;
                            end
                        
                4'b0011: begin
                            A <= 1;
                            B <= 1;
                            C <= 1;         
                            D <= 1;
                            E <= 0;
                            F <= 0;
                            G <= 1;
                            end
            
                4'b0100: begin
                            A <= 0;
                            B <= 1;
                            C <= 1;         
                            D <= 0;
                            E <= 0;
                            F <= 1;
                            G <= 1;
                            end
                        
                4'b0101: begin
                            A <= 1;
                            B <= 0;
                            C <= 1;         
                            D <= 1;
                            E <= 0;
                            F <= 1;
                            G <= 1;
                            end
                        
                4'b0110: begin
                            A <= 1;
                            B <= 0;
                            C <= 1;         
                            D <= 1;
                            E <= 1;
                            F <= 1;
                            G <= 1;
                            end
                        
                4'b0111: begin
                            A <= 1;
                            B <= 1;
                            C <= 1;         
                            D <= 0;
                            E <= 0;
                            F <= 0;
                            G <= 0;
                            end
                        
                4'b1000: begin
                            A <= 1;
                            B <= 1;
                            C <= 1;     
                            D <= 1;
                            E <= 1;
                            F <= 1;
                            G <= 1;
                            end
                        
                4'b1001: begin
                            A <= 1;
                            B <= 1;
                            C <= 1;     
                            D <= 1;
                            E <= 0;
                            F <= 1;
                            G <= 1;
                            end
                        
                default: begin
                            A <= 0;
                            B <= 1;
                            C <= 1;     
                            D <= 0;
                            E <= 1;
                            F <= 1;
                            G <= 1;
                            end     
        
            endcase
            
        end                             
        
endmodule                       
            
        
module mod_10_top( clk, led_a, led_b, led_c, led_d, led_e, led_f, led_g );

    input clk;

    output led_a;
    output led_b;
    output led_c;
    output led_d;
    output led_e;
    output led_f;
    output led_g;

    reg [9:0] counter;

    reg [3:0] seven_segment_digit;

    assign led_a = state_a;
    assign led_b = state_b;
    assign led_c = state_c;
    assign led_d = state_d;
    assign led_e = state_e;
    assign led_f = state_f;
    assign led_g = state_g; 
    
    
    /*-------------END DECLARATIONS----------------*/
        
    BCD_sevseg inst_one( clk, seven_segment_digit, state_a, state_b, state_c, state_d, state_e, state_f, state_g);
    
    always @(posedge clk) begin
        counter <= counter + 1;
        end
    
    always @(posedge counter[8]) begin
        
        for(seven_segment_digit = 4'b0000; seven_segment_digit < 4'b1010; seven_segment_digit = seven_segment_digit + 4'b0001) begin
            end
        end
endmodule


  [1]: https://i.stack.imgur.com/1mJBH.png

Answer 1

您将错误的信号连接到测试台模块 mod_10_II_sim 中的 BCD_sevseg 实例。在测试台中，您只切换 clk 信号，而不切换 clock 信号。

变化：

BCD_sevseg inst_one(
    .clock(clock),

至：

BCD_sevseg inst_one(
    .clock(clk),

您应该会在所有模块的所有实例中看到一个时钟在切换。

注意：您应该显式声明所有 state_ 信号，因为我的模拟器给了我编译错误。

wire state_a;
wire state_b;
// etc.

如何正确实例化模块并将寄存器传递给它

How to properly instantiate a module and pass registers to it

verilog

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