ERROR:Xst:1534 - Sequential logic for node <rx_data> appears to be controlled by multiple clocks

Question

我是VHDL新手，正在编写用于接收串行数据的程序，它依赖于2个时钟和一个RESET信号。一个是FPGA的主源时钟，一个是外部SPI主时钟。

写的是这样的：

    process(reset, main_clk, ext_clk)               
    begin
        if(reset = '0') then
        rx_data <= x"0000";
            elsif(chip_sel = '0') then
                if(ext_clk'event and ext_clk = '1') then    
--              rx_data <= rx_data;
                    if(main_clk'event and main_clk = '1') then
                    --- receiving data serially

但 Xilinx 工具出现错误：

ERROR:Xst:1534 - Sequential logic for node <rx_data> appears to be controlled by multiple clocks.

如何克服这个错误？

Answer 1

这是因为您在工具用来推断时钟的 ext_clk 和 main_clk 上使用了 'event。您的设计应该只对 main_clk 和 reset 敏感。德

ERROR:Xst:1534 - Sequential logic for node <rx_data> appears to be controlled by multiple clocks

ERROR:Xst:1534 - Sequential logic for node <rx_data> appears to be controlled by multiple clocks

spi

vhdl