我的具有以下图表和真相 Table 的 Prolog 代码是否正确?

Is my Prolog Code with the following Diagram and Truth Table correct?

我有以下电路图:

我也有以下真理table写在我制作的图表的Prolog中:

mygate(1,1,1,1,1).
mygate(1,1,1,0,1).
mygate(1,1,0,0,1).
mygate(1,1,0,1,1).
mygate(1,0,1,1,0).
mygate(1,0,1,0,0).
mygate(1,0,0,1,0).
mygate(1,0,0,0,1).
mygate(0,1,1,1,0).
mygate(0,1,1,0,0).
mygate(0,1,0,1,0).
mygate(0,1,0,0,1).
mygate(0,0,1,1,0).
mygate(0,0,1,0,0).
mygate(0,0,0,1,0).
mygate(0,0,0,0,1).

根据图解table后,我在prolog中分别做了与门、或门、非门的门:

myand(1,1,1).
myand(0,1,0).
myand(1,0,0).
myand(0,0,0).

myor(1,0,1).
myor(0,1,1).
myor(0,0,0).

mynot(0,1).
mynot(1,0).

然后我有以下电路根据图表确定这个真理的所有可能答案table:

circuit(W,X,Y,Z,F) :-
  myand(W,X,T1),
  mynot(Y,T2),
  myor(X,T2,T3),
  myand(T1,T3,T4),
  myor(Y,Z,T5),
  mynot(T5,T6),
  myor(T4,T6,F).

我觉得我做对了。但是,在 运行 电路(W,X,Y,Z,F)规则之后,我得到了我的序言代码的示例输出,即:

?- circuit(W, X, Y, Z, F).
W = X, X = Y, Y = Z, Z = 0,
F = 1 ;

W = X, X = Y, Y = F, F = 0,
Z = 1 ;

W = X, X = Z, Z = F, F = 0,
Y = 1 ;

W = X, X = F, F = 0,
Y = Z, Z = 1 ;

W = Y, Y = Z, Z = 0,
X = F, F = 1 ;

W = Y, Y = F, F = 0,
X = Z, Z = 1 ;

W = Z, Z = F, F = 0,
X = Y, Y = 1 ;

W = F, F = 0,
X = Y, Y = Z, Z = 1 ;

W = F, F = 1,
X = Y, Y = Z, Z = 0 ;

W = Z, Z = 1,
X = Y, Y = F, F = 0 ;

W = Y, Y = 1,
X = Z, Z = F, F = 0 ;

W = Y, Y = Z, Z = 1,
X = F, F = 0 ;

W = X, X = F, F = 1,
Y = Z, Z = 0 ;

W = X, X = Z, Z = F, F = 1,
Y = 0 ;

W = X, X = Y, Y = F, F = 1,
Z = 0 ;

W = X, X = Y, Y = Z, Z = F, F = 1.

但是,当我 运行 我的 Prolog 程序时,我得到以下输出:

?- circuit(W,X,Y,Z,F).
W = X, X = Y, Y = F, F = 1,
Z = 0 ;

W = Z, Z = F, F = 0,
X = Y, Y = 1 ;

W = X, X = Y, Y = F, F = 0,
Z = 1 ;

W = X, X = Y, Y = Z, Z = 0,
F = 1 ;

W = X, X = Z, Z = F, F = 0,
Y = 1 ;

W = Z, Z = 1,
X = Y, Y = F, F = 0 ;

W = F, F = 1,
X = Y, Y = Z, Z = 0 ;

W = Y, Y = 1,
X = Z, Z = F, F = 0.

如您所见,我得到的所有输出都是正确的。但是,我的输出缺少几个我应该有的输出。我已经检查了一切。我确保我列出了所有的门和门,我的真相的所有可能解决方案 table,基本上所有我能想到检查的东西。

我的 Prolog 代码得到的输出是正确的,还是我遗漏了什么?

如有任何帮助,我们将不胜感激。谢谢!

你漏掉了一个事实:

myor(1,1,1).

快速测试:

test :- forall(mygate(W,X,Y,Z, F0), (
  circuit(W,X,Y,Z, F1), F0=F1
  -> true
  ;  writeln(mismatch(W,X,Y,Z, F0,F1))
  )).