VHDL 中的上升沿 LED 计数器问题

Question

总的来说，我是 fpga 和 VHDL 的新手（我正在使用 fpga aprox。现在 2 周了）。我正在尝试创建一个按顺序点亮 LED 的项目。首先，我为按钮制作了一个下降沿检测器。然后我为 LED 创建了一个 std_logic_vector。但是我无法在下降沿检测中检测到信号变化。因此我无法更改 LED 状态。有我的模拟测试台。我不知道发生了什么。感谢您的回答，抱歉我的英语不好。

代码：

library ieee;
use ieee.std_logic_1164.all;

entity sequential_led is
end sequential_led;

architecture seq_led of sequential_led is
    signal clk : std_logic := '0';
    --signal rst : std_logic := '1';
    --signal rstb : std_logic := '1';
    signal i : natural := 0;
    signal dus_next : std_logic := '0';
    signal dusen : std_logic := '0';    
    signal button : std_logic := '0';
    signal led : std_logic_vector(7 downto 0);
begin
    clk <= not clk after 1 ns;
    button <= not button after 2 ns;
    falling: 
    process begin
    if rising_edge(clk) then
        dus_next <= button;
    end if;
    wait for 100 ns;
    end process falling;
    dusen <= (not button) and dus_next;
    
    led_changes:
    process begin
    if dusen = '1' then
        i <= i + 1;
        if i = 7 then
            i <= 0;
        end if;
    end if;
    led(7-i) <= '0';
    led(i) <= '1';
    wait for 100 ns;
    end process led_changes;
    
end architecture;

Answer 1

更新：首先非常感谢 DomasAquinas 和 Martin Thompson！经过3天的工作，我终于完成了我的LED小项目。

更改：我已确保所有进程都有敏感度触发器。

For falling process I've included 'clk' signal for sensivity.

For led_change process I've included 'dusen' signal for sensivity.

代码：

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity sequential_led is
    port(
        clk     : in std_logic;
        button  : in std_logic;
        led     : out std_logic_vector(7 downto 0) := (others => '0') 
    );
    signal dus_next : std_logic;
    signal i        : natural range 0 to 7;
    signal dusen    : std_logic := '0';

end sequential_led;

architecture seq_led of sequential_led is
begin
    falling: 
    process(clk) begin
    if rising_edge(clk) then
        dus_next <= button;
    end if;
    end process falling;
    dusen <= (not button) and dus_next;
    
    led_changes:
    process(dusen) begin
    if dusen = '1' then
        i <= i + 1;
        if i = 7 then
            i <= 0;
        end if;
        led(i) <= '1';
        led(i+7) <= '0';

    end if;
    end process led_changes;
    
end architecture;

VHDL 中的上升沿 LED 计数器问题

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