Facing with error : " Illegal output or inout port connection for port 'next_key'." while try to SIMULATE the design, not COMPILE
Facing with error : " Illegal output or inout port connection for port 'next_key'." while try to SIMULATE the design, not COMPILE
我正在尝试模拟我的设计，但出现此错误：
Illegal output or inout port connection for port 'next_key'.
尽管我将 wire 连接到 output reg。我试图将 'next_key' 更改为 output wire 并使 round_counter reg 和 wire.
我什至试图让 wire 成为索引变量。我想我尝试了所有的可能性。
这是模块：
module keygen (
input clock,
input startTransition,
input [127:0] roundKeyInput,
output reg [127:0] roundKeyOutput1,
output reg [127:0] roundKeyOutput2,
output reg [127:0] roundKeyOutput3,
output reg [127:0] roundKeyOutput4,
output reg [127:0] roundKeyOutput5,
output reg [127:0] roundKeyOutput6,
output reg [127:0] roundKeyOutput7,
output reg [127:0] roundKeyOutput8,
output reg [127:0] roundKeyOutput9,
output reg [127:0] roundKeyOutput10,
output reg [127:0] roundKeyOutput0
);
reg [127:0] tempKeys [0:10];
wire [127:0] round_out [1:10];
reg [3:0] round_counter ; //to be able to increment
wire [3:0] round_counter_wire;
reg [3:0] state;
reg [3:0] IDLE = 4'd0;
reg [3:0] START_CREATE_ROUNDKEY = 4'd1;
reg [3:0] STOP_CREATE_ROUNDKEY = 4'd2;
reg [3:0] STOP = 4'd3;
initial
begin
state = 4'd0;
round_counter=4'd0;
roundKeyOutput1 = 128'd0;
roundKeyOutput2 = 128'd0;
roundKeyOutput3 = 128'd0;
roundKeyOutput4 = 128'd0;
roundKeyOutput5 = 128'd0;
roundKeyOutput6 = 128'd0;
roundKeyOutput7 = 128'd0;
roundKeyOutput8 = 128'd0;
roundKeyOutput9 = 128'd0;
roundKeyOutput10 = 128'd0;
roundKeyOutput0 = 128'd0;
tempKeys[0] = 128'd0;
tempKeys[1] = 128'd0;
tempKeys[2] = 128'd0;
tempKeys[3] = 128'd0;
tempKeys[4] = 128'd0;
tempKeys[5] = 128'd0;
tempKeys[6] = 128'd0;
tempKeys[7] = 128'd0;
tempKeys[8] = 128'd0;
tempKeys[9] = 128'd0;
tempKeys[10] = 128'd0;
end
keygenround round_key(
.initial_key(tempKeys[round_counter_wire]), //input
.clk(clock),
.enable(startTransition),
.round(round_counter),
/*****************************************************///here is the error
.next_key(round_out[round_counter_wire+4'd1]) // output reg
);
assign round_counter_wire = round_counter;
always @(posedge clock)
begin
case (state)
IDLE: begin
if (startTransition==1) begin
tempKeys[0]=roundKeyInput;
roundKeyOutput0=roundKeyInput;
state= START_CREATE_ROUNDKEY;
end
end
START_CREATE_ROUNDKEY : begin
if (round_counter<4'd10) begin
if (round_counter<4'd10 && round_counter> 4'd1) tempKeys[round_counter]=round_out[round_counter];
round_counter= round_counter+1;
state= START_CREATE_ROUNDKEY;
end else begin
state = STOP_CREATE_ROUNDKEY;
end
end
STOP_CREATE_ROUNDKEY : begin
roundKeyOutput1=tempKeys[1];
roundKeyOutput2=tempKeys[2];
roundKeyOutput3=tempKeys[3];
roundKeyOutput4=tempKeys[4];
roundKeyOutput5=tempKeys[5];
roundKeyOutput6=tempKeys[6];
roundKeyOutput7=tempKeys[7];
roundKeyOutput8=tempKeys[8];
roundKeyOutput9=tempKeys[9];
roundKeyOutput10=tempKeys[10];
end
default: begin
state =IDLE;
end
endcase
end
endmodule
keygenround 模块端口映射：
module keygenround(
input [127:0] initial_key,
input clk,
input enable,
input [3:0] round,
output reg [127:0] next_key
);
编辑：这是模拟代码：
module keygen_tb;
reg clock50MHz;
reg startTransition;
reg [127:0] inputKey;
reg [127:0] expectedValue1;
reg [127:0] expectedValue2;
reg [127:0] expectedValue3;
reg [127:0] expectedValue4;
reg [127:0] expectedValue5;
reg [127:0] expectedValue6;
reg [127:0] expectedValue7;
reg [127:0] expectedValue8;
reg [127:0] expectedValue9;
reg [127:0] expectedValue10;
reg [127:0] expectedValue0;
wire [127:0] outputKey1;
wire [127:0] outputKey2;
wire [127:0] outputKey3;
wire [127:0] outputKey4;
wire [127:0] outputKey5;
wire [127:0] outputKey6;
wire [127:0] outputKey7;
wire [127:0] outputKey8;
wire [127:0] outputKey9;
wire [127:0] outputKey10;
wire [127:0] outputKey0;
keygen dut (
.clock (clock50MHz),
.startTransition (startTransition),
.roundKeyInput (inputKey),
.roundKeyOutput0 (outputKey0),
.roundKeyOutput1 (outputKey1),
.roundKeyOutput2 (outputKey2),
.roundKeyOutput3 (outputKey3),
.roundKeyOutput4 (outputKey4),
.roundKeyOutput5 (outputKey5),
.roundKeyOutput6 (outputKey6),
.roundKeyOutput7 (outputKey7),
.roundKeyOutput8 (outputKey8),
.roundKeyOutput9 (outputKey9),
.roundKeyOutput10 (outputKey10)
);
// Creating the prameters required for the 50MHz clock, and the stoppage of the test bench.
localparam NUM_CYCLES = 1000;
localparam CLOCK_FREQ = 50000000;
real HALF_CLOCK_PERIOD = (1000000000.0 / $itor(CLOCK_FREQ)) / 2.0;
integer half_cycle = 0;
initial begin
// Set input and expected values
inputKey = 128'h000102030405060708090a0b0c0d0e0f;
expectedValue0 = 128'h000102030405060708090a0b0c0d0e0f;
expectedValue1 = 128'hd6aa74fdd2af72fadaa678f1d6ab76fe;
expectedValue2 = 128'hb692cf0b643dbdf1be9bc5006830b3fe;
expectedValue3 = 128'hb6ff744ed2c2c9bf6c590cbf0469bf41;
expectedValue4 = 128'h47f7f7bc95353e03f96c32bcfd058dfd;
expectedValue5 = 128'h3caaa3e8a99f9deb50f3af57adf622aa;
expectedValue6 = 128'h5e390f7df7a69296a7553dc10aa31f6b;
expectedValue7 = 128'h14f9701ae35fe28c440adf4d4ea9c026;
expectedValue8 = 128'h47438735a41c65b9e016baf4aebf7ad2;
expectedValue9 = 128'h549932d1f08557681093ed9cbe2c974e;
expectedValue10 = 128'h13111d7fe3944a17f307a78b4d2b30c5;
startTransition = 0;
clock50MHz = 0;
end
initial begin
// Wait 500 clock cylces before setting the startTransition high.
repeat(500) @ (posedge clock50MHz);
startTransition = 1;
end
always begin
#(HALF_CLOCK_PERIOD);
clock50MHz = ~clock50MHz;
half_cycle = half_cycle + 1;
if (half_cycle == (2 * NUM_CYCLES)) begin
// Comparing the acquired outputs with the expected outputs and printing
// the corresponding message depending on the results.
if((outputKey1 != expectedValue1) | (outputKey2 != expectedValue2) |
(outputKey3 != expectedValue3) | (outputKey4 != expectedValue4) |
(outputKey5 != expectedValue5) | (outputKey6 != expectedValue6) |
(outputKey7 != expectedValue7) | (outputKey8 != expectedValue8) |
(outputKey9 != expectedValue9) | (outputKey10 != expectedValue10) |
(outputKey0 != expectedValue0)) begin
$display("Fail \n \n",
"For the following inputs: \n",
"Input Key: %h \n \n", inputKey,
"Expected output: \n",
"Output RoundKey 0: %h \n ", expectedValue0,
"Output RoundKey 1: %h \n", expectedValue1,
"Output RoundKey 2: %h \n", expectedValue2,
"Output RoundKey 3: %h \n", expectedValue3,
"Output RoundKey 4: %h \n", expectedValue4,
"Output RoundKey 5: %h \n", expectedValue5,
"Output RoundKey 6: %h \n", expectedValue6,
"Output RoundKey 7: %h \n", expectedValue7,
"Output RoundKey 8: %h \n", expectedValue8,
"Output RoundKey 9: %h \n", expectedValue9,
"Output RoundKey 10: %h \n\n", expectedValue10,
"Aquired output: \n",
"Output RoundKey 0: %h \n ", outputKey0,
"Output RoundKey 1: %h \n", outputKey1,
"Output RoundKey 2: %h \n", outputKey2,
"Output RoundKey 3: %h \n", outputKey3,
"Output RoundKey 4: %h \n", outputKey4,
"Output RoundKey 5: %h \n", outputKey5,
"Output RoundKey 6: %h \n", outputKey6,
"Output RoundKey 7: %h \n", outputKey7,
"Output RoundKey 8: %h \n", outputKey8,
"Output RoundKey 9: %h \n", outputKey9,
"Output RoundKey 10: %h \n\n", outputKey10,
,
);
end
if((outputKey1 == expectedValue1) | (outputKey2 == expectedValue2) |
(outputKey3 == expectedValue3) | (outputKey4 == expectedValue4) |
(outputKey5 == expectedValue5) | (outputKey6 == expectedValue6) |
(outputKey7 == expectedValue7) | (outputKey8 == expectedValue8) |
(outputKey9 == expectedValue9) | (outputKey10 == expectedValue10) |
(outputKey0 == expectedValue0)) begin
$display("Pass \n \n",
"For the following inputs: \n",
"Input Key: %h \n \n", inputKey,
"Aquired output: \n",
"Output RoundKey 1: %h \n", outputKey1,
"Output RoundKey 2: %h \n", outputKey2,
"Output RoundKey 3: %h \n", outputKey3,
"Output RoundKey 4: %h \n", outputKey4,
"Output RoundKey 5: %h \n", outputKey5,
"Output RoundKey 6: %h \n", outputKey6,
"Output RoundKey 7: %h \n", outputKey7,
"Output RoundKey 8: %h \n", outputKey8,
"Output RoundKey 9: %h \n", outputKey9,
"Output RoundKey 10: %h \n", outputKey10,
"Output RoundKey 11: %h \n \n", outputKey0,
);
end
$stop;
end
end
endmodule
您的问题不在于 round_counter 是一个变量 (reg)，而是模块的输出端口不能连接到具有 non-constant 选择索引的表达式。输出端口就像一个连续赋值，同样的规则适用于它的 LHS——LHS 上的索引必须是常量。就好像你写了代码
assign round_out[round_counter+1] = next_key;
如果round_counter为0，当round_counter增加到1时round_out[1]保留什么值？那并不代表任何真正的硬件。
在不知道您正在寻找什么行为的情况下，我能给出的最佳建议是声明一个 next_key 线路，并将 round_out 更改为一个 reg。并将对 round_out[round_counter+1] <= next_key 的赋值移动到始终 @(posedge clock) 块中。
wire [127:0] next_key;
reg [127:0] round_out [1:10];
reg [3:0] round_counter ; //to be able to increment
...
keygenround round_key(
.initial_key(tempKeys[round_counter_wire]), //input
.clk(clock),
.enable(startTransition),
.round(round_counter),
.next_key(next_key) // output wire
);
always @(posedge clock)
begin
round_out[round_counter+1] <= next_key;
case (state)
...
我正在尝试模拟我的设计，但出现此错误：
Illegal output or inout port connection for port 'next_key'.
尽管我将 wire 连接到 output reg。我试图将 'next_key' 更改为 output wire 并使 round_counter reg 和 wire.
我什至试图让 wire 成为索引变量。我想我尝试了所有的可能性。
这是模块：
module keygen (
input clock,
input startTransition,
input [127:0] roundKeyInput,
output reg [127:0] roundKeyOutput1,
output reg [127:0] roundKeyOutput2,
output reg [127:0] roundKeyOutput3,
output reg [127:0] roundKeyOutput4,
output reg [127:0] roundKeyOutput5,
output reg [127:0] roundKeyOutput6,
output reg [127:0] roundKeyOutput7,
output reg [127:0] roundKeyOutput8,
output reg [127:0] roundKeyOutput9,
output reg [127:0] roundKeyOutput10,
output reg [127:0] roundKeyOutput0
);
reg [127:0] tempKeys [0:10];
wire [127:0] round_out [1:10];
reg [3:0] round_counter ; //to be able to increment
wire [3:0] round_counter_wire;
reg [3:0] state;
reg [3:0] IDLE = 4'd0;
reg [3:0] START_CREATE_ROUNDKEY = 4'd1;
reg [3:0] STOP_CREATE_ROUNDKEY = 4'd2;
reg [3:0] STOP = 4'd3;
initial
begin
state = 4'd0;
round_counter=4'd0;
roundKeyOutput1 = 128'd0;
roundKeyOutput2 = 128'd0;
roundKeyOutput3 = 128'd0;
roundKeyOutput4 = 128'd0;
roundKeyOutput5 = 128'd0;
roundKeyOutput6 = 128'd0;
roundKeyOutput7 = 128'd0;
roundKeyOutput8 = 128'd0;
roundKeyOutput9 = 128'd0;
roundKeyOutput10 = 128'd0;
roundKeyOutput0 = 128'd0;
tempKeys[0] = 128'd0;
tempKeys[1] = 128'd0;
tempKeys[2] = 128'd0;
tempKeys[3] = 128'd0;
tempKeys[4] = 128'd0;
tempKeys[5] = 128'd0;
tempKeys[6] = 128'd0;
tempKeys[7] = 128'd0;
tempKeys[8] = 128'd0;
tempKeys[9] = 128'd0;
tempKeys[10] = 128'd0;
end
keygenround round_key(
.initial_key(tempKeys[round_counter_wire]), //input
.clk(clock),
.enable(startTransition),
.round(round_counter),
/*****************************************************///here is the error
.next_key(round_out[round_counter_wire+4'd1]) // output reg
);
assign round_counter_wire = round_counter;
always @(posedge clock)
begin
case (state)
IDLE: begin
if (startTransition==1) begin
tempKeys[0]=roundKeyInput;
roundKeyOutput0=roundKeyInput;
state= START_CREATE_ROUNDKEY;
end
end
START_CREATE_ROUNDKEY : begin
if (round_counter<4'd10) begin
if (round_counter<4'd10 && round_counter> 4'd1) tempKeys[round_counter]=round_out[round_counter];
round_counter= round_counter+1;
state= START_CREATE_ROUNDKEY;
end else begin
state = STOP_CREATE_ROUNDKEY;
end
end
STOP_CREATE_ROUNDKEY : begin
roundKeyOutput1=tempKeys[1];
roundKeyOutput2=tempKeys[2];
roundKeyOutput3=tempKeys[3];
roundKeyOutput4=tempKeys[4];
roundKeyOutput5=tempKeys[5];
roundKeyOutput6=tempKeys[6];
roundKeyOutput7=tempKeys[7];
roundKeyOutput8=tempKeys[8];
roundKeyOutput9=tempKeys[9];
roundKeyOutput10=tempKeys[10];
end
default: begin
state =IDLE;
end
endcase
end
endmodule
keygenround 模块端口映射：
module keygenround(
input [127:0] initial_key,
input clk,
input enable,
input [3:0] round,
output reg [127:0] next_key
);
编辑：这是模拟代码：
module keygen_tb;
reg clock50MHz;
reg startTransition;
reg [127:0] inputKey;
reg [127:0] expectedValue1;
reg [127:0] expectedValue2;
reg [127:0] expectedValue3;
reg [127:0] expectedValue4;
reg [127:0] expectedValue5;
reg [127:0] expectedValue6;
reg [127:0] expectedValue7;
reg [127:0] expectedValue8;
reg [127:0] expectedValue9;
reg [127:0] expectedValue10;
reg [127:0] expectedValue0;
wire [127:0] outputKey1;
wire [127:0] outputKey2;
wire [127:0] outputKey3;
wire [127:0] outputKey4;
wire [127:0] outputKey5;
wire [127:0] outputKey6;
wire [127:0] outputKey7;
wire [127:0] outputKey8;
wire [127:0] outputKey9;
wire [127:0] outputKey10;
wire [127:0] outputKey0;
keygen dut (
.clock (clock50MHz),
.startTransition (startTransition),
.roundKeyInput (inputKey),
.roundKeyOutput0 (outputKey0),
.roundKeyOutput1 (outputKey1),
.roundKeyOutput2 (outputKey2),
.roundKeyOutput3 (outputKey3),
.roundKeyOutput4 (outputKey4),
.roundKeyOutput5 (outputKey5),
.roundKeyOutput6 (outputKey6),
.roundKeyOutput7 (outputKey7),
.roundKeyOutput8 (outputKey8),
.roundKeyOutput9 (outputKey9),
.roundKeyOutput10 (outputKey10)
);
// Creating the prameters required for the 50MHz clock, and the stoppage of the test bench.
localparam NUM_CYCLES = 1000;
localparam CLOCK_FREQ = 50000000;
real HALF_CLOCK_PERIOD = (1000000000.0 / $itor(CLOCK_FREQ)) / 2.0;
integer half_cycle = 0;
initial begin
// Set input and expected values
inputKey = 128'h000102030405060708090a0b0c0d0e0f;
expectedValue0 = 128'h000102030405060708090a0b0c0d0e0f;
expectedValue1 = 128'hd6aa74fdd2af72fadaa678f1d6ab76fe;
expectedValue2 = 128'hb692cf0b643dbdf1be9bc5006830b3fe;
expectedValue3 = 128'hb6ff744ed2c2c9bf6c590cbf0469bf41;
expectedValue4 = 128'h47f7f7bc95353e03f96c32bcfd058dfd;
expectedValue5 = 128'h3caaa3e8a99f9deb50f3af57adf622aa;
expectedValue6 = 128'h5e390f7df7a69296a7553dc10aa31f6b;
expectedValue7 = 128'h14f9701ae35fe28c440adf4d4ea9c026;
expectedValue8 = 128'h47438735a41c65b9e016baf4aebf7ad2;
expectedValue9 = 128'h549932d1f08557681093ed9cbe2c974e;
expectedValue10 = 128'h13111d7fe3944a17f307a78b4d2b30c5;
startTransition = 0;
clock50MHz = 0;
end
initial begin
// Wait 500 clock cylces before setting the startTransition high.
repeat(500) @ (posedge clock50MHz);
startTransition = 1;
end
always begin
#(HALF_CLOCK_PERIOD);
clock50MHz = ~clock50MHz;
half_cycle = half_cycle + 1;
if (half_cycle == (2 * NUM_CYCLES)) begin
// Comparing the acquired outputs with the expected outputs and printing
// the corresponding message depending on the results.
if((outputKey1 != expectedValue1) | (outputKey2 != expectedValue2) |
(outputKey3 != expectedValue3) | (outputKey4 != expectedValue4) |
(outputKey5 != expectedValue5) | (outputKey6 != expectedValue6) |
(outputKey7 != expectedValue7) | (outputKey8 != expectedValue8) |
(outputKey9 != expectedValue9) | (outputKey10 != expectedValue10) |
(outputKey0 != expectedValue0)) begin
$display("Fail \n \n",
"For the following inputs: \n",
"Input Key: %h \n \n", inputKey,
"Expected output: \n",
"Output RoundKey 0: %h \n ", expectedValue0,
"Output RoundKey 1: %h \n", expectedValue1,
"Output RoundKey 2: %h \n", expectedValue2,
"Output RoundKey 3: %h \n", expectedValue3,
"Output RoundKey 4: %h \n", expectedValue4,
"Output RoundKey 5: %h \n", expectedValue5,
"Output RoundKey 6: %h \n", expectedValue6,
"Output RoundKey 7: %h \n", expectedValue7,
"Output RoundKey 8: %h \n", expectedValue8,
"Output RoundKey 9: %h \n", expectedValue9,
"Output RoundKey 10: %h \n\n", expectedValue10,
"Aquired output: \n",
"Output RoundKey 0: %h \n ", outputKey0,
"Output RoundKey 1: %h \n", outputKey1,
"Output RoundKey 2: %h \n", outputKey2,
"Output RoundKey 3: %h \n", outputKey3,
"Output RoundKey 4: %h \n", outputKey4,
"Output RoundKey 5: %h \n", outputKey5,
"Output RoundKey 6: %h \n", outputKey6,
"Output RoundKey 7: %h \n", outputKey7,
"Output RoundKey 8: %h \n", outputKey8,
"Output RoundKey 9: %h \n", outputKey9,
"Output RoundKey 10: %h \n\n", outputKey10,
,
);
end
if((outputKey1 == expectedValue1) | (outputKey2 == expectedValue2) |
(outputKey3 == expectedValue3) | (outputKey4 == expectedValue4) |
(outputKey5 == expectedValue5) | (outputKey6 == expectedValue6) |
(outputKey7 == expectedValue7) | (outputKey8 == expectedValue8) |
(outputKey9 == expectedValue9) | (outputKey10 == expectedValue10) |
(outputKey0 == expectedValue0)) begin
$display("Pass \n \n",
"For the following inputs: \n",
"Input Key: %h \n \n", inputKey,
"Aquired output: \n",
"Output RoundKey 1: %h \n", outputKey1,
"Output RoundKey 2: %h \n", outputKey2,
"Output RoundKey 3: %h \n", outputKey3,
"Output RoundKey 4: %h \n", outputKey4,
"Output RoundKey 5: %h \n", outputKey5,
"Output RoundKey 6: %h \n", outputKey6,
"Output RoundKey 7: %h \n", outputKey7,
"Output RoundKey 8: %h \n", outputKey8,
"Output RoundKey 9: %h \n", outputKey9,
"Output RoundKey 10: %h \n", outputKey10,
"Output RoundKey 11: %h \n \n", outputKey0,
);
end
$stop;
end
end
endmodule
您的问题不在于 round_counter 是一个变量 (reg)，而是模块的输出端口不能连接到具有 non-constant 选择索引的表达式。输出端口就像一个连续赋值，同样的规则适用于它的 LHS——LHS 上的索引必须是常量。就好像你写了代码
assign round_out[round_counter+1] = next_key;
如果round_counter为0，当round_counter增加到1时round_out[1]保留什么值？那并不代表任何真正的硬件。
在不知道您正在寻找什么行为的情况下，我能给出的最佳建议是声明一个 next_key 线路，并将 round_out 更改为一个 reg。并将对 round_out[round_counter+1] <= next_key 的赋值移动到始终 @(posedge clock) 块中。
wire [127:0] next_key;
reg [127:0] round_out [1:10];
reg [3:0] round_counter ; //to be able to increment
...
keygenround round_key(
.initial_key(tempKeys[round_counter_wire]), //input
.clk(clock),
.enable(startTransition),
.round(round_counter),
.next_key(next_key) // output wire
);
always @(posedge clock)
begin
round_out[round_counter+1] <= next_key;
case (state)
...