当我设计 cpu 使用 fpga 时，发现有太多类型 "IOB" 的绑定组件适合此设备

Question

我使用 ISE 14.7 并使用 vhdl 设计 cpu。映射时：

Blockquote Pack:2309 - Too many bonded comps of type "IOB" found to fit this device. Pack:18 - The design is too large for the given device and package. Please check the Design Summary section to see which resource requirement for your design exceeds the resources available in the device. NOTE: An NCD file will still be generated to allow you to examine the mapped design. This file is intended for evaluation use only, and will not process successfully through PAR. This mapped NCD file can be used to evaluate how the design's logic has been mapped into FPGA logic resources. It can also be used to analyze preliminary, logic-level (pre-route) timing with one of the Xilinx static timing analysis tools (TRCE or Timing Analyzer).

这是我的杯子实体：

entity cpu is  port (
RST : in std_logic;
CLK : in std_logic;
ABUS : out std_logic_vector(15 downto 0);
DBUS : inout std_logic_vector(15 downto 0);
nMREQ : out std_logic;
nRD : out std_logic;
nWR : out std_logic;
nBHE : out std_logic;
nBLE : out std_logic;
nPRD : out std_logic;
nPWR : out std_logic;
nPERQ : out std_logic;
IOAD : out std_logic_vector(1 downto 0);
IODB : inout std_logic_vector(7 downto 0);

ir : out std_logic_vector(15 downto 0) ;

tABUS : out std_logic_vector(15 downto 0);
tDBUS : out std_logic_vector(15 downto 0);
tnMREQ : out std_logic;
tnRD : out std_logic;
tnWR : out std_logic;
tnBHE : out std_logic;
tnBLE : out std_logic);
signal tmpABUS :  std_logic_vector(15 downto 0);
signal tmpnMREQ :  std_logic;
signal tmpnRD :  std_logic;
signal tmpnWR :  std_logic;
signal tmpnBHE :  std_logic;
signal tmpnBLE :  std_logic;
signal tmpnPRD :  std_logic;
signal tmpnPWR :  std_logic;
signal tmpnPERQ :  std_logic;
end entity; -- cpu

在设计摘要中：我使用 129 个 IOB，但总数是 158。我哪里错了？谢谢。对不起我的英语。

Answer 1

我好傻！！！

我只是将 entity 中的信号声明移动到 architecture。

一切正常，虽然我不知道为什么会出现一些IOBs错误。

谢谢大家

Answer 2

此错误是在执行 MAP 期间生成的。这意味着所选的 FPGA 板没有足够的 IO 缓冲区用于物理引脚。简而言之，您确实 FPGA 板上的物理引脚不足 。如果设计只是一个模块，需要连接到Top Module下，您可以忽略这个错误，因为模块之间的数据通信不需要IO缓冲区。

当我设计 cpu 使用 fpga 时，发现有太多类型 "IOB" 的绑定组件适合此设备

Too many bonded comps of type "IOB" found to fit this device when I design a cpu use fpga

vhdl

fpga