Verilog Error: "Syntax in assignment statement l-value." when writing a simple alu

Question

我在这段简单的 MIPS alu 函数模拟器代码中找不到语法错误。错误出现在case 6'b001000: // addi:

的else

ALU_.v:112: syntax error ALU_.v:113: Syntax in assignment statement l-value.

这是我的代码：

module alu(instruction, regA, regB, result, flags);

input[31:0] instruction, regA, regB; 
output[31:0] result;
output[2:0] flags; 

reg[5:0] opcode, func;
reg[4:0] rs, rt;
reg[15:0] immidiate;
reg[31:0] signeximm, zeroeximm;
reg[31:0] regC;
reg[2:0] flagout;

assign result = regC[31:0];
assign flags = flagout[2:0];

always @(instruction,regA,regB)
begin
    opcode = instruction[31:26];
    rs = instruction[25:21];
    rt = instruction[20:16];
    func = instruction[5:0];
    immidiate = instruction[15:0];
    signeximm = {{16{immidiate[15]}},immidiate};
    zeroeximm = {{16{1'b0}},immidiate};
    case(opcode)
        6'b000000: // R-type
            case(func)
                6'b100000: // add
                    begin
                        regC = $signed(regA) + $signed(regB);
                        flagout[2] = ((~regA[31])&(~regB[31])&regC[31])|(regA[31]&regB[31]&(~regC[31]));
                    end
                6'b100001: // addu
                    begin
                        regC = regA + regB;
                    end
                6'b100100: // and
                    begin
                        regC = regA & regB;
                    end                
                6'b100111: // nor
                    begin
                        regC = regA ~| regB;
                    end
                6'b100101: // or
                    begin
                        regC = regA | regB;
                    end
                6'b000000: // sll
                    begin
                        if(rt) regC = regB << instruction[10:6];
                        else regC = regA << instruction[10:6];
                    end
                6'b000100: // sllv
                    begin
                        if(rt) regC = regB << regA;
                        else regC = regA << regB;
                    end
                6'b101010: // slt
                    begin
                        if(rt) regC = ($signed(regA) < $signed(regB));
                        else regC = ($signed(regB) < $signed(regA));
                        flagout[1] = regC[0];
                    end
                6'b101011: // sltu
                    begin
                        if(rt) regC = (regA < regB);
                        else regC = (regB < regA);
                        flagout[1] = regC[0];
                    end
                6'b000011: // sra
                    begin
                        if(rt) regC = regB >>> instruction[10:6];
                        else regC = regA >>> instruction[10:6];
                    end
                6'b000111: // srav
                    begin
                        if(rt) regC = regB >>> regA;
                        else regC = regA >>> regB;
                    end
                6'b000010: // srl
                    begin
                        if(rt) regC = regB >> instruction[10:6];
                        else regC = regA >> instruction[10:6];
                    end
                6'b000110: // srlv
                    begin
                        if(rt) regC = regB >> regA;
                        else regC = regA >> regB;
                    end
                6'b100010: // sub
                    begin
                        if(rt) regC = $signed(regA) - $signed(regB);
                        else regC = $signed(regB) - $signed(regA);
                    end
                6'b100011: // subu
                    begin
                        if(rt) regC = regA - regB;
                        else regC = regB - regA;
                    end
                6'b100110: // xor
                    begin
                        regC = regA ^ regB;
                    end
            endcase
        6'b001000: // addi
            begin
                if(rt) 
                regC = $signed(regA) + $signed(signeximm);
                flagout[2] = ((~regA[31])&(~signeximm[31])&regC[31])|(regA[31]&signeximm[31]&(~regC[31]));
                else 
                regC = $signed(regB) + $signed(signeximm);
                flagout[2] = ((~regB[31])&(~signeximm[31])&regC[31])|(regB[31]&signeximm[31]&(~regC[31]));
            end
        6'b001001: // addiu
            begin
                if(rt) regC = regA + signeximm;
                else regC = regB + signeximm;
            end
        6'b001100: // andi
            begin
                if(rt) regC = regA & zeroeximm;
                else regC = regB & zeroeximm;
            end
        6'b000100: // beq
            begin
                regC = signeximm << 2;
                flagout[0] = (regA == regB);
            end
        6'b000101: // bne
            begin
                regC = signeximm << 2;
                flagout[0] = (regA != regB);
            end
        6'b100011: // lw
            begin
                if(rt) regC = regA + immidiate;
                else regC = regB + immidiate;
            end
        6'b001101: // ori
            begin
                if(rt) regC = regA | zeroeximm;
                else regC = regB | zeroeximm;
            end
        6'b001010: // slti
            begin
                if(rt) regC = $signed(regA) < $signed(signeximm);
                else regC = $signed(regB) < $signed(signeximm);
                flagout[1] = regC[0];
            end
        6'b001011: // sltiu
            begin
                if(rt) regC = regA < signeximm;
                else regC = regB < signeximm;
                flagout[1] = regC[0];
            end
        6'b101011: // sw
            begin
                if(rt) regC = regA + immidiate;
                else regC = regB + immidiate;
            end
        6'b001110: // xori
            begin
                if(rt) regC = regA ^ zeroeximm;
                else regC = regB ^ zeroeximm;
            end
        default:
            begin
                regC = 32'bx;
                flagout = 3'bx;
            end
    endcase
end

endmodule

这个错误出现在编译过程中，所以我没有机会检查当前代码中是否还有其他问题。

Answer 1

有两个编码错误：
以这种方式修复它们

这是一个错误的 nor 表达式

regC = ~(regA | regB);
缺少 begin/end 对

像这样

if(rt)
  begin
  regC = $signed(regA) + $signed(signeximm);
  flagout[2] = ((~regA[31])&(~signeximm[31])&regC[31])|(regA[31]&signeximm[31]&(~regC[31]));
  end
 else
 begin
   regC = $signed(regB) + $signed(signeximm);
   flagout[2] = ((~regB[31])&(~signeximm[31])&regC[31])|(regB[31]&signeximm[31]&(~regC[31]));
 end

Verilog Error: "Syntax in assignment statement l-value." when writing a simple alu

Verilog Error: "Syntax in assignment statement l-value." when writing a simple alu

verilog

syntax-error

iverilog