How to fix "Error: Expected expression of type std_ulogic"?

Question

我正在学习 VHDL，我尝试用两个文件实现“adder_array_generic_tree”，第一个文件“user_defined_type_pkg.vhd”包含：

library IEEE;
use ieee.numeric_std.all;

package user_defined_type_pkg is
    type signed_vector is array (natural range<>) of signed;
end package;

第二个文件“adder_array_generic_tree.vhd”包含：

library IEEE;
use IEEE.numeric_std.all;
use ieee.math_real.all;
use work.user_defined_type_pkg.all;

entity adder_array_generic_tree is
    generic (
        NUM_INPUTS: natural := 10;
        NUM_BITS: natural := 7);
    port (
        x: in signed_vector(0 to NUM_INPUTS-1)(NUM_BITS-1 downto 0);
        sum: out signed(NUM_BITS + integer(ceil(log2(real(NUM_INPUTS))))-1 downto 0));
end adder_array_generic_tree;

architecture tree_type_generic of adder_array_generic_tree is
    constant LAYERS: natural := integer(ceil(log2(real(NUM_INPUTS))));
    constant PWR_OF_TWO: natural := 2**LAYERS;
    alias EXTRA_BITS: natural is LAYERS;
begin
    process (all)
        variable accum: signed_vector(0 to PWR_OF_TWO-1)(NUM_BITS+EXTRA_BITS-1 downto 0);
    begin
        loop1: for i in 0 to NUM_INPUTS-1 loop
            accum(i) := resize(x(i), NUM_BITS+EXTRA_BITS);
        end loop loop1;
        accum(NUM_INPUTS to PWR_OF_TWO-1) := (others => (others => '0'));
        
        loop2: for j in 1 to LAYERS loop
            loop3: for i in 0 to PWR_OF_TWO/(2**j)-1 loop
                accum(i) := accum(2*i) + accum(2*i+1);
            end loop loop3;
        end loop loop2;
        sum <= accum(0);
    end process;
end tree_type_generic;

但是，第二个文件的第26行有问题：

accum(NUM_INPUTS to PWR_OF_TWO-1) := (others => (others => '0'));

'0' 上带有红色下划线的 Vivado 表示“错误：类型为 std_ulogic 的预期表达式”。文件类型为VHDL 2008，采用xa7s6cpga196-2I.

Answer 1

您没有包含包 ieee.std_logic_1164，因此 std_ulogic 不可见。 '0' 的唯一可见选项是 std.standard 包中的 character 或 bit，因此 ieee.numeric_std.signed 的错误是 ieee.std_logic_1164.std_logic 的数组。

要修复，只需添加以下行：

use ieee.std_logic_1164.all

在文件的顶部。

How to fix "Error: Expected expression of type std_ulogic"?

How to fix "Error: Expected expression of type std_ulogic"?

vhdl

vivado