在 Xilinx 中测试 Assert 语句时出错
Error while testing Assert statement in Xilinx
我目前收到此错误
ERROR:HDLCompiler:1731 -
Line ...: found '0' definitions of operator "=", cannot determine
exact overloaded matching definition for "="
我的最后 2 个 Assert 语句如下所示(PulseOutput 和 IsCounting)。它不喜欢那个等号,但是您如何测试 1 位信号值?它上面的断言 (CountTemp) 没有收到任何错误。有什么想法吗?!
signal CountTemp : std_logic_vector(15 downto 0) := (others => '0');
signal PulseOutput : std_logic;
signal IsCounting : std_logic;
--------------------------------------------------------------
stim_proc:process
begin
SystemClear <= '1';
-- hold reset state for 10 ns, then test 3 signals, then hold for additional 10 ns
wait for 10 ns;
assert (CountTemp = X"0000") report "CountTemp should equal 0 when System Clear is active" severity ERROR;
assert (PulseOutput = 0) report "PulseOutput should equal 0 when System Clear is active" severity ERROR;
assert (IsCounting = 0) report "IsCounting should equal 0 when System Clear is active" severity ERROR;
wait for 10 ns;
std_logic
位用撇号 '
表示,请注意,这在 VHDL 中也称为 tick。因此,例如在您的代码中:
stim_proc:process
begin
SystemClear <= '1';
-- hold reset state for 10 ns, then test 3 signals, then hold for additional 10 ns
wait for 10 ns;
assert (CountTemp = X"0000") report "CountTemp should equal 0 when System Clear is active" severity ERROR;
assert (PulseOutput = '0') report "PulseOutput should equal 0 when System Clear is active" severity ERROR;
assert (IsCounting = '0') report "IsCounting should equal 0 when System Clear is active" severity ERROR;
wait for 10 ns;
我目前收到此错误
ERROR:HDLCompiler:1731 - Line ...: found '0' definitions of operator "=", cannot determine exact overloaded matching definition for "="
我的最后 2 个 Assert 语句如下所示(PulseOutput 和 IsCounting)。它不喜欢那个等号,但是您如何测试 1 位信号值?它上面的断言 (CountTemp) 没有收到任何错误。有什么想法吗?!
signal CountTemp : std_logic_vector(15 downto 0) := (others => '0');
signal PulseOutput : std_logic;
signal IsCounting : std_logic;
--------------------------------------------------------------
stim_proc:process
begin
SystemClear <= '1';
-- hold reset state for 10 ns, then test 3 signals, then hold for additional 10 ns
wait for 10 ns;
assert (CountTemp = X"0000") report "CountTemp should equal 0 when System Clear is active" severity ERROR;
assert (PulseOutput = 0) report "PulseOutput should equal 0 when System Clear is active" severity ERROR;
assert (IsCounting = 0) report "IsCounting should equal 0 when System Clear is active" severity ERROR;
wait for 10 ns;
std_logic
位用撇号 '
表示,请注意,这在 VHDL 中也称为 tick。因此,例如在您的代码中:
stim_proc:process
begin
SystemClear <= '1';
-- hold reset state for 10 ns, then test 3 signals, then hold for additional 10 ns
wait for 10 ns;
assert (CountTemp = X"0000") report "CountTemp should equal 0 when System Clear is active" severity ERROR;
assert (PulseOutput = '0') report "PulseOutput should equal 0 when System Clear is active" severity ERROR;
assert (IsCounting = '0') report "IsCounting should equal 0 when System Clear is active" severity ERROR;
wait for 10 ns;