为什么我的移位寄存器在一个时钟而不是 4 个时钟内显示结果？

Question

这是我的 dff 和多路复用器和移位寄存器的代码，它应该在 4 个时钟内丰富输出，但它在一个时钟内完成，我无法自己修复它。这是我的 dff 代码：

use IEEE.STD_LOGIC_1164.ALL;


entity DFLipFlop is
    Port ( d : in  STD_LOGIC;
           clock : in  STD_LOGIC;
              reset : in STD_LOGIC;
           q : out  STD_LOGIC);
end DFLipFlop;

architecture Behavioral of DFLipFlop is

begin
process(clock,reset)
begin
if(reset ='1')then
q <= '0';
elsif(CLOCK='1' and CLOCK'EVENT)then
q <= d;
end if;
end process;
end Behavioral;

这是我的多路复用器代码：

-- Company: 
-- Engineer: 
-- 
-- Create Date:    08:37:48 04/27/2022 
-- Design Name: 
-- Module Name:    multiplexer - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity multiplexer is
    Port ( DataIn : in  STD_LOGIC;
           P_in : in  STD_LOGIC;
           Selector : in  STD_LOGIC;
           Output : out  STD_LOGIC);
end multiplexer;

architecture Behavioral of multiplexer is

begin

process(Selector)
begin 
   
    if Selector = '0' then
       Output <= DataIn ;

    else        
        OutPut <= P_in ;
   
    end if;
 end process;


end Behavioral;

这是我的移位寄存器代码：

-- Company: 
-- Engineer: 
-- 
-- Create Date:    08:35:05 04/27/2022 
-- Design Name: 
-- Module Name:    shiftRegister - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity shiftRegister is
    Port ( DataIn : in  STD_LOGIC;
           Selector : in  STD_LOGIC;
           P_in : in  STD_LOGIC_VECTOR (3 downto 0);
           Clk : in  STD_LOGIC;
           OutPut : out  STD_LOGIC);
end shiftRegister;

architecture structural of shiftRegister is

component DFLipFlop is
    Port ( d : in  STD_LOGIC;
           clock : in  STD_LOGIC;
              reset : in STD_LOGIC;
           q : out  STD_LOGIC);
end component DFLipFlop;

component multiplexer is
    Port ( DataIn : in  STD_LOGIC;
           P_in : in  STD_LOGIC;
           Selector : in  STD_LOGIC;
           Output : out  STD_LOGIC);
end component multiplexer;


signal DFFOutput :  STD_LOGIC_VECTOR(3 downto 0);
signal MuxOutput :  STD_LOGIC_VECTOR(3 downto 0);

begin 

multiplexer0 : multiplexer Port map( DataIn => DataIn , P_in => P_in(3) , Selector => Selector , Output =>  MuxOutput(0) );
dff_interface0 : DFLipFlop port map( d => MuxOutput(0) , clock => Clk , reset => '0' , q => DFFOutput(0));

multiplexer1 : multiplexer Port map( DataIn => DFFOutput(0) , P_in => P_in(2) , Selector => Selector , Output =>  MuxOutput(1) );
dff_interface1 : DFLipFlop port map( d => MuxOutput(1) , clock => Clk  , reset => '0' , q => DFFOutput(1));

multiplexer2 : multiplexer Port map( DataIn => DFFOutput(1) , P_in => P_in(1) , Selector => Selector , Output =>  MuxOutput(2) );
dff_interface2 : DFLipFlop port map( d => MuxOutput(2) , clock => Clk  , reset => '0' , q => DFFOutput(2));

multiplexer3 : multiplexer Port map( DataIn => DFFOutput(2) , P_in => P_in(0) , Selector => Selector , Output =>  MuxOutput(3) );
dff_interface3 : DFLipFlop port map( d => MuxOutput(3) , clock => Clk  , reset => '0' , q => Output);

end structural;

这是我的测试台：

-- Company: 
-- Engineer:
--
-- Create Date:   09:12:38 04/27/2022
-- Design Name:   
-- Module Name:   C:/Users/ABTIN/Documents/amirkabir un/term 4/Computer Architecture/Lab/HW8/HW8/TestBench.vhd
-- Project Name:  HW8
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: shiftRegister
-- 
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
 
ENTITY TestBench IS
END TestBench;
 
ARCHITECTURE behavior OF TestBench IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT shiftRegister
    PORT(
         DataIn : IN  std_logic;
         Selector : IN  std_logic;
         P_in : IN  std_logic_vector(3 downto 0);
         Clk : IN  std_logic;
         OutPut : OUT  std_logic
        );
    END COMPONENT;
    

   --Inputs
   signal DataIn : std_logic := '0';
   signal Selector : std_logic := '0';
   signal P_in : std_logic_vector(3 downto 0) := "1011";
   signal Clk : std_logic := '0';

    --Outputs
   signal OutPut : std_logic;

   -- Clock period definitions
   constant Clk_period : time := 5 ns;
 
BEGIN
 
    -- Instantiate the Unit Under Test (UUT)
   uut: shiftRegister PORT MAP (
          DataIn => DataIn,
          Selector => Selector,
          P_in => P_in,
          Clk => Clk,
          OutPut => OutPut
        );

   -- Clock process definitions
   Clk_process :process
   begin
        Clk <= '0';
        wait for Clk_period/2;
        Clk <= '1';
        wait for Clk_period/2;
   end process;
 

   -- Stimulus process
   stim_proc: process
   begin        
      -- hold reset state for 100 ns.


      wait for Clk_period*10;
      DataIn <= '0' ; P_in <= "1011" ; Selector <= '1' ;wait for Clk_period*1;
      DataIn <= '1' ; P_in <= "1001"  ;wait for Clk_period*2;
      
      -- insert stimulus here 

      wait;
   end process;

END;

我不知道问题出在哪里。请帮忙

Answer 1

您的数据输入信号不会在单个时钟内通过移位寄存器传播。

查看 this simulation 时，您可以看到预加载数据的高位在光标所在的时钟边沿加载。行为与代码一致。

详细解释是：

在光标处，Selector 为 1，这意味着多路复用器将 select P_in 值
因为 DFF 获得了 P_in 值，它在光标处加载它并且 P_in 的第 4 位是 1 所以 DFFOutput 也变成了 1

如果您想在 shift-register 中传播一个 1，您应该首先重置它（将其设置为零），然后在输入中给它一个 1。

您应该在测试平台开始时使用正确的重置。这样您的设计就会进入已知状态。

在您的测试台中，您为信号分配了初始值，但在敏感度列表中使用了它们（罪魁祸首是 selector）。因此，多路复用器的输出未定义，因为该过程不是由信号变化触发的。

您应该将测试台更改为如下所示：

-- hold reset state for 100 ns.
     wait for Clk_period * 10;
     selector <= '0'; -- this assignment triggers the multiplexer processes
     p_in <= "1011";

我还强烈建议模拟您的整个设计并探索内部信号（我看到您使用 Vivado，它有一个集成模拟器；否则，如果您需要，英特尔会提供免费的 Modelsim 许可证）。

如果您想使用 Vivado 模拟器，请查看 UG937。

要获取如何在 Vivado 中实现特定组件的示例，您还可以查看 Synthesis Guide (UG901)。有一个用于移位寄存器以优化利用 FPGA 资源的实现示例（其他 FPGA 制造商也有类似的指南，请在您最喜欢的搜索引擎中查找 综合指南）。

对于Vivado，在工具 > 语言模板.

下也有集成的代码示例

为什么我的移位寄存器在一个时钟而不是 4 个时钟内显示结果？

why my shift register show the result in one clock instead of 4?

vhdl

shift-register