我不能在 VHDL 中递增一个无符号数

Question

所以我尝试了我在互联网上遇到的主要方法，但它从未奏效，我尝试了很多不同的方法，但似乎无法使它起作用。当它应该进行第一次递增时，无符号计数器将从 000000 变为 00000X，然后在第二次递增时它将变为 XXXXXX。

我的代码就在下面：

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity Horloge_3s is
    Port ( rst_n : in STD_LOGIC;
           clk : in STD_LOGIC;
           start_3s : in STD_LOGIC;
           etat_systeme : in STD_LOGIC_VECTOR (1 downto 0);
           end_3s : out STD_LOGIC);
end Horloge_3s;

architecture Behavioral of Horloge_3s is

type states is (notCounting, counting, newGame);
signal current_state, future_state : states;
signal counter, counterInc : unsigned (28 downto 0) := (others => '0');

begin

registre : process(clk, rst_n)
begin
    if rst_n = '0' then
        counter <= "00000000000000000000000000000";
        current_state <= notCounting;
    elsif rising_edge(clk) then
        --if current_state = counting then
            --counter <= counter + 1;
       -- end if; 
        current_state <= future_state;
    end if;
end process;

compteur : process(current_state, counter)
begin
        
    if current_state = counting then
        if counter = "10001111000011010001100000000" then
            end_3s <= '1';
        else
            end_3s <= '0';
            counter <= counterInc + 1;
        end if;
    elsif current_state = notCounting then
        counter <= "00000000000000000000000000000";
        end_3s <= '0';
    elsif current_state = newGame then
        counter <= "00000000000000000000000000000";
        end_3s <= '0';
    end if;

end process;

combiEtats : process(current_state, start_3s, etat_systeme)
begin
    
    if etat_systeme = "00" then
        future_state <= newGame;
    else
        case current_state is
            when notCounting => 
                if start_3s = '1' then
                    future_state <= counting;
                else
                    future_state <= notCounting;
                end if;
            when counting =>
                if counter = "10001111000011010001100000000" then
                    future_state <= notCounting;
                else
                    future_state <= counting;
                end if;
            when newGame => 
                future_state <= notCounting;
            when others => 
                future_state <= notCounting;
        end case;
    end if;
         
end process;      

end Behavioral;

Answer 1

您在多个进程中分配了 counter，因此它有多个驱动程序。最初这是可行的，因为当您将 counter 初始化为 0 时它们都在 counter 上驱动“0”，但是当您添加一个时，进程 registre 从重置驱动 0 并且进程 compteur 是现在驾驶 1，因此你有 0 和 1 相互驾驶导致 'X'。解决方案是仅从单个进程驱动 counter。

由于这是一个计数器，您确实应该从时钟进程而不是组合进程中驱动它。在组合过程中有一个计数器会导致它在0次无限循环中计数。

我不能在 VHDL 中递增一个无符号数

I can't increment an unsigned number in VHDL

unsigned

increment

vhdl