在测试台中将 std_logic 转换为整数?
Converting std_logic to integer within testbench?
我正在尝试在 ISim 的控制台 Window 中的特定时间 return CLK 信号的值(在我下面的代码中显示,7.5ns)。我收到此错误:
ERROR:HDLCompiler:258 - "saved project.." Line 91: Cannot convert type
std_logic to type unsigned
我已将此转换( integer'image(to_integer(unsigned((generic_signal)))); )与 std_logic_vectors 并且效果很好,但是这个不行。 CLK 值是 0 或 1,我只想在给定时间 return 该值。你知道更有效的方法吗?你碰巧知道一个 link 在那里我可以看到更多的方法来 return 变量值使用 'image
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-----------------------------------------------------------
-- Component Declaration for the Unit Under Test
-----------------------------------------------------------
component SyncPosEdge port(
SYS_CLK : in std_logic;
InputSignal : in std_logic;
SyncOutputSignal : out std_logic);
end component;
-----------------------------------------------------------
-- Inputs
-----------------------------------------------------------
signal SYS_CLK : std_logic := '0';
signal InputSignal : std_logic := '0';
-----------------------------------------------------------
-- Outputs
-----------------------------------------------------------
signal SyncOutputSignal : std_logic;
-----------------------------------------------------------
-- Clock period definitions
-----------------------------------------------------------
constant SYS_CLK_period : time := 5 ns;
constant InputPeriod : time := 15 ns;
begin
-----------------------------------------------------------
-- Instantiate the Unit Under Test
-----------------------------------------------------------
uut:SyncPosEdge port map(
SYS_CLK => SYS_CLK,
InputSignal => InputSignal,
SyncOutputSignal => SyncOutputSignal);
-----------------------------------------------------------
-- Clock process definitions
-----------------------------------------------------------
SYS_CLK_process:process
begin
SYS_CLK <= '0';
wait for SYS_CLK_period / 2;
SYS_CLK <= '1';
wait for SYS_CLK_period / 2;
end process SYS_CLK_process;
-----------------------------------------------------------
-- Generate Input Signal
-----------------------------------------------------------
InputGen:process
begin
InputSignal <= '0';
wait for InputPeriod / 2;
InputSignal <= '1';
wait for InputPeriod / 2;
end process;
-----------------------------------------------------------
-- Stimulus process
-----------------------------------------------------------
stim_proc:process
begin
wait for 7.5 ns;
report "SYS_CLK: " & integer'image(to_integer(unsigned((SYS_CLK))));
wait;
end process stim_proc;
您可以使用 image
属性轻松打印 std_logic
:
report "SYS_CLK: " & std_logic'image(SYS_CLK);
我正在尝试在 ISim 的控制台 Window 中的特定时间 return CLK 信号的值(在我下面的代码中显示,7.5ns)。我收到此错误:
ERROR:HDLCompiler:258 - "saved project.." Line 91: Cannot convert type std_logic to type unsigned
我已将此转换( integer'image(to_integer(unsigned((generic_signal)))); )与 std_logic_vectors 并且效果很好,但是这个不行。 CLK 值是 0 或 1,我只想在给定时间 return 该值。你知道更有效的方法吗?你碰巧知道一个 link 在那里我可以看到更多的方法来 return 变量值使用 'image
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-----------------------------------------------------------
-- Component Declaration for the Unit Under Test
-----------------------------------------------------------
component SyncPosEdge port(
SYS_CLK : in std_logic;
InputSignal : in std_logic;
SyncOutputSignal : out std_logic);
end component;
-----------------------------------------------------------
-- Inputs
-----------------------------------------------------------
signal SYS_CLK : std_logic := '0';
signal InputSignal : std_logic := '0';
-----------------------------------------------------------
-- Outputs
-----------------------------------------------------------
signal SyncOutputSignal : std_logic;
-----------------------------------------------------------
-- Clock period definitions
-----------------------------------------------------------
constant SYS_CLK_period : time := 5 ns;
constant InputPeriod : time := 15 ns;
begin
-----------------------------------------------------------
-- Instantiate the Unit Under Test
-----------------------------------------------------------
uut:SyncPosEdge port map(
SYS_CLK => SYS_CLK,
InputSignal => InputSignal,
SyncOutputSignal => SyncOutputSignal);
-----------------------------------------------------------
-- Clock process definitions
-----------------------------------------------------------
SYS_CLK_process:process
begin
SYS_CLK <= '0';
wait for SYS_CLK_period / 2;
SYS_CLK <= '1';
wait for SYS_CLK_period / 2;
end process SYS_CLK_process;
-----------------------------------------------------------
-- Generate Input Signal
-----------------------------------------------------------
InputGen:process
begin
InputSignal <= '0';
wait for InputPeriod / 2;
InputSignal <= '1';
wait for InputPeriod / 2;
end process;
-----------------------------------------------------------
-- Stimulus process
-----------------------------------------------------------
stim_proc:process
begin
wait for 7.5 ns;
report "SYS_CLK: " & integer'image(to_integer(unsigned((SYS_CLK))));
wait;
end process stim_proc;
您可以使用 image
属性轻松打印 std_logic
:
report "SYS_CLK: " & std_logic'image(SYS_CLK);