我无法理解的 VHDL 新手错误

Question

我很难弄清楚我做错了什么。有人可以看一下并指出正确的方向吗？

Library ieee;
USE ieee.std_logic_1164.all; 
----------------------------------------- 
ENTITY muxOuts IS 
PORT 
(X,CLK,SET : in std_logic;
Y : out std_logic_vector(1 downto 0);
Z2 : out std_logic); 
END ENTITY; 

ARCHITECTURE circuitDesign OF muxOuts IS
type state_type is (ST0,ST1,ST2);
signal PS,NS : state_type;

BEGIN
 sync_proc: process(CLK,NS,SET)
 begin
 if (set = 1 )then
 PS <= ST2;
 elsif (rising_edge(CLK)) then
 PS <= NS;
 end if;

 end process sync_proc;
 comb_proc: process(PS,X)
 begin
 case PS is
 when Z2 => 0 end process; 
 end when ST0 =>; -- items regarding state ST0
 Z2 <= 0; -- Mealy output always 0
 if (X = 0) then NS <= ST0;
 else NS <= ST1;
 end if;
 when ST1 => -- items regarding state fST1
 Z2 <= 0; -- Mealy output always 0
 if (X = 0) then NS <= ST0;
 else NS <= ST2;
 end if;
 when ST2 => -- items regarding state ST2
 -- Mealy output handled in the if statement
 if(X=0)then NS<=ST0; Z2<=0;
 else NS<=ST2; Z2<=1;
 endif;
 end when others => -- the catch fall condition
 Z2 <= f1; NS f< ST0;
 end case;
 end process comb_proc;

 -- faking some state variable outputs
 with PS select
 Y <= 00 when ST0,
 10 when ST1,
 11 when ST2,
 00 when others;
 end muxOuts;


 END ARCHITECTURE  circuitDesign OF mux0uts;

我收到这些错误消息：

COMP96 Compile Architecture "circuitDesign" of Entity "muxOuts"
COMP96 ERROR COMP96_0019: "Keyword 'end' expected." "testbench.vhd" 28 13
COMP96 ERROR COMP96_0019: "Keyword 'case' expected." "testbench.vhd" 28 15
COMP96 ERROR COMP96_0015: "';' expected." "testbench.vhd" 29 6
COMP96 ERROR COMP96_0016: "Design unit declaration expected." "testbench.vhd" 29 11
COMP96 Compile Architecture "circuitDesign" of Entity "mux0uts"
COMP96 ERROR COMP96_0019: "Keyword 'is' expected." "testbench.vhd" 58 43
COMP96 ERROR COMP96_0019: "Keyword 'begin' expected." "testbench.vhd" 58 43
COMP96 Compile failure 6 Errors 0 Warnings  Analysis time :  40.0 [ms]

这是怎么回事？我这辈子都弄不明白。

Answer 1

请正确缩进您的代码并仔细检查您的语法，有许多微不足道的错误，通过正确的缩进和带有语法突出显示的编辑器更容易发现。

其中一些：

case PS is
    when Z2 => 0 end process;
end when ST0 =>; -- items regarding state ST0

这显然是错误的语法，我不确定你想要实现什么，但我想这就是你想要的：

case PS is
    when ST0 => -- No reference to Z2 (which is not a state), no end process, no random end and no semicolon

还有：

    endif;
end when others => -- the catch fall condition
    Z2 <= f1; NS f< ST0;
end case;

可能是这样的

    end if; -- Needs a space...
when others =>
    Z2 <= f1;
    Ns <= ST0; -- Assignation is <=, not < (compare)

最后：

    end muxOuts;


END ARCHITECTURE  circuitDesign OF mux0uts;

它是 end circuitDesign; 或 end architecture circuitDesign;。

我无法理解的 VHDL 新手错误

VHDL newbie errors i cannot understand

vhdl