如何将 array_type（数组）输入转换为 std_logic_vector？

Question

 library IEEE;
 use IEEE.STD_LOGIC_1164.ALL;
 use IEEE.NUMERIC_STD.ALL;

 entity shift_unit is
 Port ( clk: in std_logic;
          a_0 : in  STD_LOGIC_VECTOR(15 downto 0);
       a_1 : in  STD_LOGIC_VECTOR(15 downto 0);
       b_0 : in  STD_LOGIC_VECTOR(15 downto 0);
       b_1 : in  STD_LOGIC_VECTOR(15 downto 0);
       a064 : out  STD_LOGIC_VECTOR(15 downto 0);
          a164 : out  STD_LOGIC_VECTOR(15 downto 0);
       c083,c036 : out  STD_LOGIC_VECTOR(15 downto 0);
          c183,c136 : out  STD_LOGIC_VECTOR(15 downto 0));
 end shift_unit;

 architecture Behavioral of shift_unit is
 type array_type is array (0 to 1) of std_logic_vector(15 downto 0);

 Component SA is
 port( clk: in std_logic;    
  bi: in std_logic_vector(15 downto 0);
  c83: out std_logic_vector(15 downto 0);
    c36: out std_logic_vector(15 downto 0));        
  end Component;
 signal b ,c_083,c_036: array_type;
  begin

      process(clk)
      variable i: integer:=0;
       begin
      if(rising_edge(clk)) then
       elsif(i=0) then
         b(i)<=b_0; 
         i:=i+1;
       elsif(i=1) then
          b(i)<=b_1;
          i:=0;
       end if;
     end process;

       SA_GEN: for I in 0 to 1 generate
         SA0 : SA port map(clk,b,c_083(I),c_036(I));  --error. Line 65
       end generate SA_GEN;

       end Behavioral;

组件 SA 是

entity SA is
port( clk: in std_logic;
  bi: in std_logic_vector(15 downto 0);
  c83: out std_logic_vector(15 downto 0);
    c36: out std_logic_vector(15 downto 0));        
end SA;

当我检查 Syntex 时出现错误 ERROR:HDLParsers:820 - "shift_unit_pk.vhdl" 第 65 行。实际端口类型与 SA 端口类型不兼容。

此处b、c083和c036属于array_type，SA在std_logic_vector中有i/p和o/p端口。我试图将它转换为 std_logic_vector 然后映射到 SA，但它给出了同样的错误。那么我该如何做这个映射/类型转换。

Answer 1

b这里是一个数组SA0 : SA port map(clk,b,c083(I),c036(I));是32位的，一个数组

但是在SA，你需要bi: in std_logic_vector(15 downto 0)；是16位，一个向量。

~~SA0 : SA port map(clk,b(I),c083(I),c036(I)); 可能有效。~~

c083是一个向量，你的意思是c_083？

SA0 : SA port map(clk,b(I),c_083(I),c_036(I));

Answer 2

这是您的代码，其中包含一些修复和改进：

library IEEE;
use     IEEE.STD_LOGIC_1164.ALL;
use     IEEE.NUMERIC_STD.ALL;

entity shift_unit is
  Port (
    clk: in std_logic;
    a_0 : in  STD_LOGIC_VECTOR(15 downto 0);
    a_1 : in  STD_LOGIC_VECTOR(15 downto 0);
    b_0 : in  STD_LOGIC_VECTOR(15 downto 0);
    b_1 : in  STD_LOGIC_VECTOR(15 downto 0);
    a064 : out  STD_LOGIC_VECTOR(15 downto 0);
    a164 : out  STD_LOGIC_VECTOR(15 downto 0);
    c083,c036 : out  STD_LOGIC_VECTOR(15 downto 0);
    c183,c136 : out  STD_LOGIC_VECTOR(15 downto 0)
  );
end shift_unit;

architecture Behavioral of shift_unit is
  type array_type is array (0 to 1) of std_logic_vector(15 downto 0);

  Component SA is
    port(
      clk: in std_logic;    
      bi: in std_logic_vector(15 downto 0);
      c83: out std_logic_vector(15 downto 0);
      c36: out std_logic_vector(15 downto 0)
    );
  end Component;

  signal b ,c_083,c_036: array_type;
begin

  process(clk)
    variable i: std_logic := '0';
  begin
    if(rising_edge(clk)) then
      if(i = '0') then
        b(0) <= b_0; 
      else
        b(1) <= b_1;
      end if;
      i <= not i;
    end if;
  end process;

  SA_GEN: for I in 0 to 1 generate
    SA0 : SA
      port map(
        clk => clk,
        bi =>  b(I),
        c83 => c_083(I),
        c36 => c_036(I)
      );
  end generate SA_GEN;
end;

如果您对高级 std_logic_vector、std_logic_vector_vector 和 std_logic_matrix 处理的 VHDL 类型和函数感兴趣，请查看此 post：https://codereview.stackexchange.com/questions/73708/vhdl-mux-in-need-of-generics/73794#73794

如何将 array_type（数组）输入转换为 std_logic_vector？

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