VHDL信号分配混乱
VHDL Signal Assignment Confusion
我在学习VHDL时遇到了一个我找不到答案的问题。我理解以下示例以及结果为 7 的原因：
architecture SIGN of EXAMPLE is
signal TRIGGER, RESULT: integer := 0;
signal signal1: integer :=1;
signal signal2: integer :=2;
signal signal3: integer :=3;
begin
process
begin
wait on TRIGGER;
signal1 <= signal2;
signal2 <= signal1 + signal3;
signal3 <= signal2;
RESULT <= signal1 + signal2 + signal3;
end process;
end SIGN;
但是，如果我将 signal1 放入敏感列表会怎样？还是所有的信号？
首先，如果为进程创建了敏感列表，则必须删除或注释掉 wait on TRIGGER 语句，因为具有敏感列表的进程不能同时具有 wait 语句。
如果signal1是进程敏感列表，那么进程初始是运行，然后只要signal1有变化就重新运行。
默认分配后的值，或基于进程 运行 的分配，适用于 signal1、signal2、signal3 和 RESULT：
Default.: 1, 2, 3, 0
First...: 2, 4, 2, 6
Re-run 1: 4, 4, 4, 8
Re-run 2: 4, 8, 4, 12
请记住，根据增量循环仿真模型，信号分配在过程完成后才会生效。
由于re-运行1和2之间signal1没有变化，那么这个过程就不是运行了，RESULT的值因此是 12，从最后一个 运行.
如果signal1和signal2在进程敏感列表中，那么每个进程运行都会改变其中一个信号，因此进程会继续重新运行 直到达到模拟器增量循环迭代限制，否则 integer 数据类型将出现超出范围的值，导致值不再发生变化。
您在挥手致意，却没有展示完整的示例以及您提出的更改建议。
目前，为什么RESULT = 0？
你为什么不模拟这一切？
entity example is
end entity;
architecture SIGN of EXAMPLE is
signal TRIGGER, RESULT: integer := 0;
signal signal1: integer :=1;
signal signal2: integer :=2;
signal signal3: integer :=3;
begin
process
begin
wait on TRIGGER;
signal1 <= signal2;
signal2 <= signal1 + signal3;
signal3 <= signal2;
RESULT <= signal1 + signal2 + signal3;
end process;
monitor:
process(RESULT)
begin
report "RESULT = " & integer'image(RESULT);
end process;
end SIGN;
sign.vhdl:21:9:@0ms:(report note): RESULT = 0
entity example is
end entity;
architecture SIGN of EXAMPLE is
signal TRIGGER, RESULT: integer := 0;
signal signal1: integer :=1;
signal signal2: integer :=2;
signal signal3: integer :=3;
begin
process (signal1)
begin
-- wait on TRIGGER;
signal1 <= signal2;
signal2 <= signal1 + signal3;
signal3 <= signal2;
RESULT <= signal1 + signal2 + signal3;
end process;
monitor:
process(RESULT)
begin
report "RESULT = " & integer'image(RESULT);
end process;
end SIGN;
sign.vhdl:21:9:@0ms:(report note): RESULT = 0
sign.vhdl:21:9:@0ms:(report note): RESULT = 6
sign.vhdl:21:9:@0ms:(report note): RESULT = 8
sign.vhdl:21:9:@0ms:(report note): RESULT = 12
entity example is
end entity;
architecture SIGN of EXAMPLE is
signal TRIGGER, RESULT: integer := 0;
signal signal1: integer :=1;
signal signal2: integer :=2;
signal signal3: integer :=3;
begin
process (signal1, signal2, signal3)
begin
-- wait on TRIGGER;
signal1 <= signal2;
signal2 <= signal1 + signal3;
signal3 <= signal2;
RESULT <= signal1 + signal2 + signal3;
end process;
monitor:
process(RESULT)
begin
report "RESULT = " & integer'image(RESULT);
end process;
end SIGN;
sign.vhdl:21:9:@0ms:(report note): RESULT = 0
sign.vhdl:21:9:@0ms:(report note): RESULT = 6
sign.vhdl:21:9:@0ms:(report note): RESULT = 8
sign.vhdl:21:9:@0ms:(report note): RESULT = 12
sign.vhdl:21:9:@0ms:(report note): RESULT = 16
sign.vhdl:21:9:@0ms:(report note): RESULT = 24
sign.vhdl:21:9:@0ms:(report note): RESULT = 32
sign.vhdl:21:9:@0ms:(report note): RESULT = 48
sign.vhdl:21:9:@0ms:(report note): RESULT = 64
sign.vhdl:21:9:@0ms:(report note): RESULT = 96
sign.vhdl:21:9:@0ms:(report note): RESULT = 128
sign.vhdl:21:9:@0ms:(report note): RESULT = 192
sign.vhdl:21:9:@0ms:(report note): RESULT = 256
sign.vhdl:21:9:@0ms:(report note): RESULT = 384
sign.vhdl:21:9:@0ms:(report note): RESULT = 512
sign.vhdl:21:9:@0ms:(report note): RESULT = 768
sign.vhdl:21:9:@0ms:(report note): RESULT = 1024
sign.vhdl:21:9:@0ms:(report note): RESULT = 1536
sign.vhdl:21:9:@0ms:(report note): RESULT = 2048
sign.vhdl:21:9:@0ms:(report note): RESULT = 3072
sign.vhdl:21:9:@0ms:(report note): RESULT = 4096
sign.vhdl:21:9:@0ms:(report note): RESULT = 6144
sign.vhdl:21:9:@0ms:(report note): RESULT = 8192
sign.vhdl:21:9:@0ms:(report note): RESULT = 12288
sign.vhdl:21:9:@0ms:(report note): RESULT = 16384
sign.vhdl:21:9:@0ms:(report note): RESULT = 24576
sign.vhdl:21:9:@0ms:(report note): RESULT = 32768
sign.vhdl:21:9:@0ms:(report note): RESULT = 49152
sign.vhdl:21:9:@0ms:(report note): RESULT = 65536
sign.vhdl:21:9:@0ms:(report note): RESULT = 98304
sign.vhdl:21:9:@0ms:(report note): RESULT = 131072
sign.vhdl:21:9:@0ms:(report note): RESULT = 196608
sign.vhdl:21:9:@0ms:(report note): RESULT = 262144
sign.vhdl:21:9:@0ms:(report note): RESULT = 393216
sign.vhdl:21:9:@0ms:(report note): RESULT = 524288
sign.vhdl:21:9:@0ms:(report note): RESULT = 786432
sign.vhdl:21:9:@0ms:(report note): RESULT = 1048576
sign.vhdl:21:9:@0ms:(report note): RESULT = 1572864
sign.vhdl:21:9:@0ms:(report note): RESULT = 2097152
sign.vhdl:21:9:@0ms:(report note): RESULT = 3145728
sign.vhdl:21:9:@0ms:(report note): RESULT = 4194304
sign.vhdl:21:9:@0ms:(report note): RESULT = 6291456
sign.vhdl:21:9:@0ms:(report note): RESULT = 8388608
sign.vhdl:21:9:@0ms:(report note): RESULT = 12582912
sign.vhdl:21:9:@0ms:(report note): RESULT = 16777216
sign.vhdl:21:9:@0ms:(report note): RESULT = 25165824
sign.vhdl:21:9:@0ms:(report note): RESULT = 33554432
sign.vhdl:21:9:@0ms:(report note): RESULT = 50331648
sign.vhdl:21:9:@0ms:(report note): RESULT = 67108864
sign.vhdl:21:9:@0ms:(report note): RESULT = 100663296
sign.vhdl:21:9:@0ms:(report note): RESULT = 134217728
sign.vhdl:21:9:@0ms:(report note): RESULT = 201326592
sign.vhdl:21:9:@0ms:(report note): RESULT = 268435456
sign.vhdl:21:9:@0ms:(report note): RESULT = 402653184
sign.vhdl:21:9:@0ms:(report note): RESULT = 536870912
sign.vhdl:21:9:@0ms:(report note): RESULT = 805306368
sign.vhdl:21:9:@0ms:(report note): RESULT = 1073741824
sign.vhdl:21:9:@0ms:(report note): RESULT = 1610612736
sign.vhdl:21:9:@0ms:(report note): RESULT = -2147483648
sign.vhdl:21:9:@0ms:(report note): RESULT = -1073741824
sign.vhdl:21:9:@0ms:(report note): RESULT = 0
sign.vhdl:21:9:@0ms:(report note): RESULT = -2147483648
sign.vhdl:21:9:@0ms:(report note): RESULT = 0
并且将 RESULT 和 TRIGGER 添加到敏感度列表会给出相同的答案。你能说说为什么吗？
值翻转实际上揭示了此 VHDL 实现中的错误。
IEEE Std 1076-2008，5.2.3 整数类型，5.2.3.1 通用，第 7 段/-1993，3.1.2 整数类型，第 7 段（注释 9.2 参考是 -1993 中的 7.2）：
The same arithmetic operators are predefined for all integer types (see 9.2). It is an error if the execution of such an operation (in particular, an implicit conversion) cannot deliver the correct result (that is, if the value corresponding to the mathematical result is not a value of the integer type).
"It is an error" 没有不正确结果的余地。对于超过 INTEGER'HIGH 的“+”运算结果，模拟应该有错误。测试声明为 INTEGER 类型的信号子类型的界限失败。
我在学习VHDL时遇到了一个我找不到答案的问题。我理解以下示例以及结果为 7 的原因：
architecture SIGN of EXAMPLE is
signal TRIGGER, RESULT: integer := 0;
signal signal1: integer :=1;
signal signal2: integer :=2;
signal signal3: integer :=3;
begin
process
begin
wait on TRIGGER;
signal1 <= signal2;
signal2 <= signal1 + signal3;
signal3 <= signal2;
RESULT <= signal1 + signal2 + signal3;
end process;
end SIGN;
但是，如果我将 signal1 放入敏感列表会怎样？还是所有的信号？
首先，如果为进程创建了敏感列表，则必须删除或注释掉 wait on TRIGGER 语句，因为具有敏感列表的进程不能同时具有 wait 语句。
如果signal1是进程敏感列表，那么进程初始是运行，然后只要signal1有变化就重新运行。
默认分配后的值，或基于进程 运行 的分配，适用于 signal1、signal2、signal3 和 RESULT：
Default.: 1, 2, 3, 0
First...: 2, 4, 2, 6
Re-run 1: 4, 4, 4, 8
Re-run 2: 4, 8, 4, 12
请记住，根据增量循环仿真模型，信号分配在过程完成后才会生效。
由于re-运行1和2之间signal1没有变化，那么这个过程就不是运行了，RESULT的值因此是 12，从最后一个 运行.
如果signal1和signal2在进程敏感列表中，那么每个进程运行都会改变其中一个信号，因此进程会继续重新运行 直到达到模拟器增量循环迭代限制，否则 integer 数据类型将出现超出范围的值，导致值不再发生变化。
您在挥手致意，却没有展示完整的示例以及您提出的更改建议。
目前，为什么RESULT = 0？
你为什么不模拟这一切？
entity example is
end entity;
architecture SIGN of EXAMPLE is
signal TRIGGER, RESULT: integer := 0;
signal signal1: integer :=1;
signal signal2: integer :=2;
signal signal3: integer :=3;
begin
process
begin
wait on TRIGGER;
signal1 <= signal2;
signal2 <= signal1 + signal3;
signal3 <= signal2;
RESULT <= signal1 + signal2 + signal3;
end process;
monitor:
process(RESULT)
begin
report "RESULT = " & integer'image(RESULT);
end process;
end SIGN;
sign.vhdl:21:9:@0ms:(report note): RESULT = 0
entity example is
end entity;
architecture SIGN of EXAMPLE is
signal TRIGGER, RESULT: integer := 0;
signal signal1: integer :=1;
signal signal2: integer :=2;
signal signal3: integer :=3;
begin
process (signal1)
begin
-- wait on TRIGGER;
signal1 <= signal2;
signal2 <= signal1 + signal3;
signal3 <= signal2;
RESULT <= signal1 + signal2 + signal3;
end process;
monitor:
process(RESULT)
begin
report "RESULT = " & integer'image(RESULT);
end process;
end SIGN;
sign.vhdl:21:9:@0ms:(report note): RESULT = 0
sign.vhdl:21:9:@0ms:(report note): RESULT = 6
sign.vhdl:21:9:@0ms:(report note): RESULT = 8
sign.vhdl:21:9:@0ms:(report note): RESULT = 12
entity example is
end entity;
architecture SIGN of EXAMPLE is
signal TRIGGER, RESULT: integer := 0;
signal signal1: integer :=1;
signal signal2: integer :=2;
signal signal3: integer :=3;
begin
process (signal1, signal2, signal3)
begin
-- wait on TRIGGER;
signal1 <= signal2;
signal2 <= signal1 + signal3;
signal3 <= signal2;
RESULT <= signal1 + signal2 + signal3;
end process;
monitor:
process(RESULT)
begin
report "RESULT = " & integer'image(RESULT);
end process;
end SIGN;
sign.vhdl:21:9:@0ms:(report note): RESULT = 0
sign.vhdl:21:9:@0ms:(report note): RESULT = 6
sign.vhdl:21:9:@0ms:(report note): RESULT = 8
sign.vhdl:21:9:@0ms:(report note): RESULT = 12
sign.vhdl:21:9:@0ms:(report note): RESULT = 16
sign.vhdl:21:9:@0ms:(report note): RESULT = 24
sign.vhdl:21:9:@0ms:(report note): RESULT = 32
sign.vhdl:21:9:@0ms:(report note): RESULT = 48
sign.vhdl:21:9:@0ms:(report note): RESULT = 64
sign.vhdl:21:9:@0ms:(report note): RESULT = 96
sign.vhdl:21:9:@0ms:(report note): RESULT = 128
sign.vhdl:21:9:@0ms:(report note): RESULT = 192
sign.vhdl:21:9:@0ms:(report note): RESULT = 256
sign.vhdl:21:9:@0ms:(report note): RESULT = 384
sign.vhdl:21:9:@0ms:(report note): RESULT = 512
sign.vhdl:21:9:@0ms:(report note): RESULT = 768
sign.vhdl:21:9:@0ms:(report note): RESULT = 1024
sign.vhdl:21:9:@0ms:(report note): RESULT = 1536
sign.vhdl:21:9:@0ms:(report note): RESULT = 2048
sign.vhdl:21:9:@0ms:(report note): RESULT = 3072
sign.vhdl:21:9:@0ms:(report note): RESULT = 4096
sign.vhdl:21:9:@0ms:(report note): RESULT = 6144
sign.vhdl:21:9:@0ms:(report note): RESULT = 8192
sign.vhdl:21:9:@0ms:(report note): RESULT = 12288
sign.vhdl:21:9:@0ms:(report note): RESULT = 16384
sign.vhdl:21:9:@0ms:(report note): RESULT = 24576
sign.vhdl:21:9:@0ms:(report note): RESULT = 32768
sign.vhdl:21:9:@0ms:(report note): RESULT = 49152
sign.vhdl:21:9:@0ms:(report note): RESULT = 65536
sign.vhdl:21:9:@0ms:(report note): RESULT = 98304
sign.vhdl:21:9:@0ms:(report note): RESULT = 131072
sign.vhdl:21:9:@0ms:(report note): RESULT = 196608
sign.vhdl:21:9:@0ms:(report note): RESULT = 262144
sign.vhdl:21:9:@0ms:(report note): RESULT = 393216
sign.vhdl:21:9:@0ms:(report note): RESULT = 524288
sign.vhdl:21:9:@0ms:(report note): RESULT = 786432
sign.vhdl:21:9:@0ms:(report note): RESULT = 1048576
sign.vhdl:21:9:@0ms:(report note): RESULT = 1572864
sign.vhdl:21:9:@0ms:(report note): RESULT = 2097152
sign.vhdl:21:9:@0ms:(report note): RESULT = 3145728
sign.vhdl:21:9:@0ms:(report note): RESULT = 4194304
sign.vhdl:21:9:@0ms:(report note): RESULT = 6291456
sign.vhdl:21:9:@0ms:(report note): RESULT = 8388608
sign.vhdl:21:9:@0ms:(report note): RESULT = 12582912
sign.vhdl:21:9:@0ms:(report note): RESULT = 16777216
sign.vhdl:21:9:@0ms:(report note): RESULT = 25165824
sign.vhdl:21:9:@0ms:(report note): RESULT = 33554432
sign.vhdl:21:9:@0ms:(report note): RESULT = 50331648
sign.vhdl:21:9:@0ms:(report note): RESULT = 67108864
sign.vhdl:21:9:@0ms:(report note): RESULT = 100663296
sign.vhdl:21:9:@0ms:(report note): RESULT = 134217728
sign.vhdl:21:9:@0ms:(report note): RESULT = 201326592
sign.vhdl:21:9:@0ms:(report note): RESULT = 268435456
sign.vhdl:21:9:@0ms:(report note): RESULT = 402653184
sign.vhdl:21:9:@0ms:(report note): RESULT = 536870912
sign.vhdl:21:9:@0ms:(report note): RESULT = 805306368
sign.vhdl:21:9:@0ms:(report note): RESULT = 1073741824
sign.vhdl:21:9:@0ms:(report note): RESULT = 1610612736
sign.vhdl:21:9:@0ms:(report note): RESULT = -2147483648
sign.vhdl:21:9:@0ms:(report note): RESULT = -1073741824
sign.vhdl:21:9:@0ms:(report note): RESULT = 0
sign.vhdl:21:9:@0ms:(report note): RESULT = -2147483648
sign.vhdl:21:9:@0ms:(report note): RESULT = 0
并且将 RESULT 和 TRIGGER 添加到敏感度列表会给出相同的答案。你能说说为什么吗？
值翻转实际上揭示了此 VHDL 实现中的错误。
IEEE Std 1076-2008，5.2.3 整数类型，5.2.3.1 通用，第 7 段/-1993，3.1.2 整数类型，第 7 段（注释 9.2 参考是 -1993 中的 7.2）：
The same arithmetic operators are predefined for all integer types (see 9.2). It is an error if the execution of such an operation (in particular, an implicit conversion) cannot deliver the correct result (that is, if the value corresponding to the mathematical result is not a value of the integer type).
"It is an error" 没有不正确结果的余地。对于超过 INTEGER'HIGH 的“+”运算结果，模拟应该有错误。测试声明为 INTEGER 类型的信号子类型的界限失败。