VHDL <b_Off_OBUF> 不完整。信号不由设计中的任何源引脚驱动

Question

我正在尝试在 Spartan-3E 开发板上编写一个非常简单的程序。我想读取滑动开关并使用滑动开关旁边的 LED 指示哪个开关处于打开位置。

这是我的代码：

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;


entity Switch is
   PORT(a,b,c,d: IN std_logic; 
     a_ON,a_Off,b_ON,b_Off,c_ON,c_Off,d_ON,d_Off: OUT std_logic);
end Switch;

architecture Behavioral of Switch is

begin
  PROCESS (a)
  begin
    if a = '1' then
      a_ON <= '1';
    else 
      a_OFF <= '1';
    end if;
 END PROCESS;   
end Behavioral;

这是我的 *.ucf 文件：

NET "a" LOC = "L13" | IOSTANDARD = LVTTL | PULLUP ;
NET "b" LOC = "L14" | IOSTANDARD = LVTTL | PULLUP ;
NET "c" LOC = "H18" | IOSTANDARD = LVTTL | PULLUP ;
NET "d" LOC = "N17" | IOSTANDARD = LVTTL | PULLUP ;

NET "d_OFF" LOC = "F9" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "d_ON" LOC = "E9" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "c_OFF" LOC = "D11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "c_ON" LOC = "C11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "b_OFF" LOC = "F11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "b_ON" LOC = "E11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "a_OFF" LOC = "E12" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "a_ON" LOC = "F12" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;

这是我得到的错误：

PhysDesignRules:368 - The signal is incomplete. The signal is not driven by any source pin in the design.

ERROR:PhysDesignRules:368 - The signal is incomplete. The signal is not driven by any source pin in the design.

ERROR:PhysDesignRules:368 - The signal is incomplete. The signal is not driven by any source pin in the design.

ERROR:PhysDesignRules:368 - The signal is incomplete. The signal is not driven by any source pin in the design.

ERROR:PhysDesignRules:368 - The signal is incomplete. The signal is not driven by any source pin in the design.

ERROR:PhysDesignRules:368 - The signal is incomplete. The signal is not driven by any source pin in the design.

WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not drive any load pins in the design.

Answer 1

您设计中的以下输出端口未连接到任何逻辑或以任何方式驱动：

b_ON,b_Off,c_ON,c_Off,d_ON,d_Off

您需要至少 '0' 驾驶它们才能通过 DRC。例如：

b_ON <= '0';

如果出于某种原因你真的不想驱动这些信号，你可以将它们设置为模式 inout，然后用 'Z':

驱动它们

port (
  b_ON : inout std_logic
);

...

b_ON <= 'Z';

VHDL <b_Off_OBUF> 不完整。信号不由设计中的任何源引脚驱动

VHDL <b_Off_OBUF> is incomplete. The signal is not driven by any source pin in the design

spartan

vhdl

xilinx

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