place_design 时钟约束 VHDL Vivado FPGA 错误

Question

所以我试图在 Vivado 中为 ZYBO FPGA 板设计一个 'vending machine' 时序电路。然而，每次我试图通过实施阶段时，我都会遇到一堆错误，主要错误是

[Place 30-58] IO placement is infeasible. Number of unplaced terminals (1) is greater than
number of available sites (0).
The following Groups of I/O terminals have not sufficient capacity: 
 IO Group: 0 with : SioStd: LVCMOS18   VCCO = 1.8 Termination: 0  TermDir:  In   RangeId: 1  
has only 0 sites available on device, but needs 1 sites.
Term: clk

我确实尝试了自动 I/O 规划，但最终所做的只是删除了引脚限制。它在那时通过了实现，但当然无法生成比特流，因为 none 端口被映射到引脚。

这是我的 VHDL 设计

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY des_src IS
    PORT (
        reset       : IN    std_logic;
        clk         : IN    std_logic;
        QDN         : IN    std_logic_vector(2 DOWNTO 0);
        PC          : OUT   std_logic_vector(1 DOWNTO 0)
    );
END des_src;

ARCHITECTURE behavioral OF des_src IS
    TYPE        statetype IS (Start, Five, Ten, Fifteen, Twenty, Twentyfive, Thirty, Thirtyfive, Fourty, Fourtyfive);
    SIGNAL      currentstate, nextstate     : statetype;
BEGIN
    fsm1:   PROCESS (QDN, currentstate)
    BEGIN
        CASE currentstate IS
                WHEN Start =>
                        PC <= "00";
                        CASE QDN IS
                                WHEN "000" =>
                                        nextstate <= Start;
                                WHEN "001" =>
                                        nextstate <= Five;
                                WHEN "010" =>
                                        nextstate <= Ten;
                                WHEN "100" =>
                                        nextstate <= Twentyfive;
                                WHEN OTHERS =>
                                        nextstate <= Start;
                         END CASE;
                WHEN Five =>
                         PC <= "00";
                         CASE QDN IS
                                 WHEN "000" =>
                                         nextstate <= Five;
                                 WHEN "001" =>
                                         nextstate <= Ten;
                                 WHEN "010" =>
                                         nextstate <= Fifteen;
                                 WHEN "100" =>
                                         nextstate <= Thirty;
                                 WHEN OTHERS =>
                                         nextstate <= Start;
                        END CASE;
                WHEN Ten =>
                        PC <= "00";
                        CASE QDN IS
                                WHEN "000" =>
                                        nextstate <= Ten;
                                WHEN "001" =>
                                        nextstate <= Fifteen;
                                WHEN "010" =>
                                        nextstate <= Twenty;
                                WHEN "100" =>
                                        nextstate <= Thirtyfive;
                                WHEN OTHERS =>
                                        nextstate <= Start;
                        END CASE;
                WHEN Fifteen =>
                        PC <= "00";
                        CASE QDN IS
                                WHEN "000" =>
                                        nextstate <=Fifteen;
                                WHEN "001" =>
                                        nextstate <= Twenty;
                                WHEN "010" =>
                                        nextstate <= Twentyfive;
                                WHEN "100" =>
                                        nextstate <= Fourty;
                                WHEN OTHERS =>
                                        nextstate <= Start;
                        END CASE;
                WHEN Twenty =>
                        PC <= "00";
                        CASE QDN IS
                                WHEN "000" =>
                                        nextstate <= Twenty;
                                WHEN "001" =>
                                        nextstate <= Twentyfive;
                                WHEN "010" =>
                                        nextstate <= Thirty;
                                WHEN "100" =>
                                        nextstate <= Fourtyfive;
                                WHEN OTHERS =>
                                        nextstate <= Start;
                        END CASE;
                WHEN Twentyfive =>
                        PC <= "10";
                        nextstate <= Start;
                WHEN Thirty =>
                        PC <= "01";
                        nextstate <= Twentyfive;
                WHEN Thirtyfive =>
                        PC <= "01";
                        nextstate <= Thirty;
                WHEN Fourty =>
                        PC <= "01";
                        nextstate <= Thirtyfive;
                WHEN Fourtyfive =>
                        PC <= "01";
                        nextstate <= Fourty;
        END CASE;
    END PROCESS;

    fsm2:   PROCESS (reset, clk)
    BEGIN
        IF (reset = '0') THEN
                currentstate <= Start;
        ELSIF (clk'EVENT) AND (clk = '1') THEN
                currentstate <= nextstate;
        END IF;
    END PROCESS;
END behavioral;

这是我的约束条件

##Buttons
##IO_L20N_T3_34
set_property IOSTANDARD LVCMOS33 [get_ports {QDN[0]}]
set_property PACKAGE_PIN R18 [get_ports {QDN[0]}]

##IO_L24N_T3_34
set_property IOSTANDARD LVCMOS33 [get_ports {QDN[1]}]
set_property PACKAGE_PIN P16 [get_ports {QDN[1]}]

##IO_L18P_T2_34
set_property IOSTANDARD LVCMOS33 [get_ports {QDN[2]}]
set_property PACKAGE_PIN V16 [get_ports {QDN[2]}]

##IO_L7P_T1_34
set_property IOSTANDARD LVCMOS33 [get_ports reset]
set_property PACKAGE_PIN Y16 [get_ports reset]

##LEDs
##IO_L23P_T3_35
set_property IOSTANDARD LVCMOS33 [get_ports {PC[0]}]
set_property PACKAGE_PIN M14 [get_ports {PC[0]}]

##IO_L23N_T3_35
set_property IOSTANDARD LVCMOS33 [get_ports {PC[1]}]
set_property PACKAGE_PIN M15 [get_ports {PC[1]}]

create_clock -period 10.000 -name clk -waveform {0.000 5.000} [get_ports clk]
set_input_delay -clock [get_clocks clk] -min -add_delay 0.000 [get_ports {QDN[*]}]
set_input_delay -clock [get_clocks clk] -max -add_delay 0.000 [get_ports {QDN[*]}]
set_input_delay -clock [get_clocks clk] -min -add_delay 0.000 [get_ports reset]
set_input_delay -clock [get_clocks clk] -max -add_delay 0.000 [get_ports reset]
set_output_delay -clock [get_clocks clk] -min -add_delay 0.000 [get_ports {PC[*]}]
set_output_delay -clock [get_clocks clk] -max -add_delay 0.000 [get_ports {PC[*]}]

我使用的是Vivado 2015.2，正在为ZYBO开发板设计。

感谢任何帮助。

编辑 2015 年 8 月 26 日

好的，我的代码大部分都可以正常工作。我能够使用

set_property PACKAGE_PIN L16 [get_ports clk]
set_property IOSTANDARD LVCMOS33 [get_ports clk]
create_clock -period 10.000 -name clk -waveform {0.000 5.000} [get_ports clk]

我的时钟。然而，这个时钟比我想要的快得多（125MHz），所以我知道我必须使用时钟分频并在约束文件中生成一个时钟，但是我需要将生成的时钟分配给一个引脚吗？有没有人对如何在我当前的 vhdl 代码中包含时钟分频器有任何提示？我只是让它成为另一个进程，并添加另一个端口，还是比这更复杂？

Answer 1

您没有为 clk 主节点分配引脚。我想 Vivado 决定它需要一个 1.8V LVCMOS 输入（可能是默认的）但是 Zybo 上没有可用的 LVCMOS 1V8 用户引脚：唯一的 1V8 bank 是 501，它已经被以太网、USB OTG 完全使用， SD 卡、UART 和按钮。正如您可能告诉 Vivado 您正在使用 Zybo，它不能单独解决这个问题。

因此，如果您有外部时钟源，请将其连接到其中一个 pmod 连接器，将相应的引脚声明为 LVCMOS3V3 并将其分配给 clk。否则，如果您希望时钟由处理系统驱动，则必须明确将 4 个 FCLK PS-to-PL 时钟之一连接到设计的 clk 输入。

在我看来，最简单的方法是将您的设计转化为 IP（参见 Vivado 文档），在块设计中实例化它，添加一个处理系统和主要的 I/Os需要接线。

place_design 时钟约束 VHDL Vivado FPGA 错误

place_design Error for clock constraint VHDL Vivado FPGA

syntax-error

vhdl

vivado