未使用 vhdl 输入

Question

我正在尝试开发一个 8 位二进制转 BCD VHDL 模块，但 Xilinx 套件正在优化我的 Bin_in 信号以始终接地。我发现其他几个线程提到了类似的问题（在不同的编码上下文中），但提供的答案似乎与未声明输出的完整真相 table 的算法有关。我还发现了一个 8 位到 BCD 转换器的示例，其算法与我的类似。如果我正确地开发了我的代码，那么只要 Bin_in 输入发生变化，过程就应该运行，所以我不明白为什么这些工具会优化它。非常感谢任何信息或帮助。

这是综合警告：

WARNING:Xst:647 - Input <Bin_in<7:1>> is never used. This port will be
preserved and left unconnected if it belongs to a top-level block or
it belongs to a sub-block and the hierarchy of this sub-block is
preserved.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.numeric_std.ALL;

entity B8_to_4BCD is
port (Bin_in : in std_logic_vector (7 downto 0);
      BCD0, BCD1, BCD2 : out std_logic_vector (3 downto 0)
     );

end entity B8_to_4BCD;

architecture Behavioral of B8_to_4BCD is

begin

--Sequential code follows, runs if Bin_in changes
process (Bin_in)
--Holders for Bin_in and output BCD
variable input : std_logic_vector (7 downto 0);
variable output : std_logic_vector (11 downto 0);

begin
    input  := Bin_in;          --Assign Bin_in to input
    output := (others => '0'); --Set output to all zeroes

    for I in 1 to 8 loop
        --Check ones for greater than or equal to 5
        if output(3 downto 0) >= "0101" then
            output(3 downto 0) := output(3 downto 0) + "0011";

        --Check tens for greater than or equal to 5
        elsif output(7 downto 4) >= "0101" then
            output(7 downto 4) := output(7 downto 4) + "0011";

        --Check hundreds for greater than or equal to 5
        elsif output(11 downto 8) >= "0101" then
            output(11 downto 8) := output(11 downto 8) + "0011";
        else

        end if;

        output := output(11 downto 1) & input(7); --Shift output left one and move input(7) into LSB
        input := input(6 downto 0) & '0';         --Shift input left one and pad with zero

    end loop;

    BCD0 <= output(3 downto 0);
    BCD1 <= output(7 downto 4);
    BCD2 <= output(11 downto 8);

end process;

end Behavioral;

Answer 1

除了 Paebbels 提出的问题，即 if 语句应该是独立的，输出左移也有问题。

以下是修正后的for循环：

    for i in 1 to 8 loop
        if output(3 downto 0) >= "0101" then
            output(3 downto 0) := output(3 downto 0) + "0011";
        end if;
        --check tens for greater than or equal to 5
        if output(7 downto 4) >= "0101" then
            output(7 downto 4) := output(7 downto 4) + "0011";
        end if;
        --check hundreds for greater than or equal to 5
        if output(11 downto 8) >= "0101" then
            output(11 downto 8) := output(11 downto 8) + "0011";            
        end if;
        output := output(10 downto 0) & input(7);       --shift output left one and move input(7) into lsb
        input := input(6 downto 0) & '0' ;              --shift input left one and pad with zero;
     end loop;

还有一个测试台：

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity bin8bcd_tb is
end entity;

architecture foo of bin8bcd_tb is
    signal bin: std_logic_vector (7 downto 0) := (others => '0');
    -- (initialized to prevent those annoying metavalue reports)

    signal bcd: std_logic_vector (11 downto 0);

begin

DUT:
    entity work.b8_to_4bcd
        port map (
            bin_in => bin,
            bcd0 => bcd(3 downto 0),
            bcd1 => bcd(7 downto 4),
            bcd2 => bcd(11 downto 8)
        );

STIMULUS:
    process

    begin
        for i in 0 to 255 loop
            bin <= std_logic_vector(to_unsigned(i,8));
            wait for 1 ns;
        end loop;
        wait for 1 ns;
        wait;
    end process;
end architecture;

给出：

（可点击）

输入二进制（基数十进制）和输出 BCD（基数十六进制）的匹配值。

您希望合成输出与模拟匹配。请注意警告告诉你 Bin_in<7:1> 没有改变，而 LSB 改变了（它会匹配你的模拟，它匹配我的）。

先仿真后综合，适合我们这些校对不顺的人。

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