如何在 4 位 ALU 设计中连接 3 个操作 select 位 - VHDL
How to concatenate 3 operation select bits in a 4-bit ALU design - VHDL
所以我一直在做这个作业，它要求我设计一个由几个位（即 S1、S0、Cin/C0（进位）和 M）控制的 4 位 ALU，具体取决于ALU 将根据 M 的值执行逻辑或算术运算。我临时设计了一个 ALU，它使用名为 'Sel' 的输入，同时我弄清楚如何获取 3 个差异输入（S0、S1、Cin/C0）的值。我不知道如何连接这 3 位。在执行逻辑运算时，我还使用“-”表示无关位。此外，由于我没有使用 3 个控制选择，所以模式 (m) 感觉是多余的。因此请忽略部分代码，因为它们没有用。
我在最后附上了一张图片，解释了预期的内容。
代码
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity codeALU is
Port ( A : in STD_LOGIC_VECTOR (3 downto 0);
B : in STD_LOGIC_VECTOR (3 downto 0);
Cin : in STD_LOGIC;
--S0 : in STD_LOGIC;
--S1 : in STD_LOGIC;
Sel : in STD_LOGIC_VECTOR (2 downto 0);
M : in STD_LOGIC;
Cout : out STD_LOGIC;
Z : out STD_LOGIC;
F : out STD_LOGIC_VECTOR (3 downto 0));
end codeALU;
architecture Behavioral of codeALU is
begin
process(A, B, M, Cin, Sel)
--variable X : STD_LOGIC_VECTOR (1 downto 0);
--variable Y : STD_LOGIC_VECTOR (2 downto 0);
variable temp : STD_LOGIC_VECTOR (4 downto 0);
variable Fx : STD_LOGIC_VECTOR (3 downto 0);
variable Cx, Zx : STD_LOGIC;
begin
--X := S1 & S0;
--Y := S1 & S0 & Cin;
Cx := '0';
Zx := '0';
if M = '0' then
Z <= '0';
case Sel is
when "00-" =>
Fx := A AND B;
Zx := '0';
when "01-" =>
Fx := A XOR B;
when "10-" =>
Fx := A OR B;
when "11-" =>
Fx := A XNOR B;
when others =>
null;
end case;
elsif M = '1' then
case Sel is
when "000" =>
temp := (B(3)&B(3 downto 1) + ('0'&A));
Fx := temp(3 downto 0);
Cx := temp(4);
when "001" =>
temp := (A(3)&A(3 downto 1) + ('0'&B));
Fx := temp(3 downto 0);
Cx := temp(4);
when "010" =>
temp := ('0'&A) + ('0'&B);
Fx := temp(3 downto 0);
Cx := temp(4);
when "011" =>
temp := ('0'&A) + ('0'&B) + ('0'&Cin);
Fx := temp(3 downto 0);
Cx := temp(4);
when "100" =>
temp := ('0'&A) + (not B);
Fx := temp(3 downto 0);
Cx := temp(4);
when "101" =>
temp := (not B) + ('0'&A) + 1;
Fx := temp(3 downto 0);
Cx := temp(4);
when "110" =>
temp := ('0'&A) + ('0'&B(3 downto 1));
Fx := temp(3 downto 0);
Cx := temp(4);
when "111" =>
temp := ('0'&B) + ('0'&A(3 downto 1));
Fx := temp(3 downto 0);
Cx := temp(4);
when others =>
null;
end case;
for i in 0 to 3 loop
Zx := Zx or Fx(i);
end loop;
Z <= not Zx;
else null;
end if;
F <= Fx;
Cout <= Cx;
end process;
end Behavioral;
测试台
![LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY test2ALU IS
END test2ALU;
ARCHITECTURE behavior OF test2ALU IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT codeALU
PORT(
A : IN std_logic_vector(3 downto 0);
B : IN std_logic_vector(3 downto 0);
Cin : IN std_logic;
Sel : IN std_logic_vector(2 downto 0);
M : IN std_logic;
Cout : OUT std_logic;
Z : OUT std_logic;
F : OUT std_logic_vector(3 downto 0)
);
END COMPONENT;
--Inputs
signal A : std_logic_vector(3 downto 0) := (others => '0');
signal B : std_logic_vector(3 downto 0) := (others => '0');
signal Cin : std_logic := '0';
signal Sel : std_logic_vector(2 downto 0) := (others => '0');
signal M : std_logic := '0';
--Outputs
signal Cout : std_logic;
signal Z : std_logic;
signal F : std_logic_vector(3 downto 0);
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: codeALU PORT MAP (
A => A,
B => B,
Cin => Cin,
Sel => Sel,
M => M,
Cout => Cout,
Z => Z,
F => F
);
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
A <= "1001";
B <= "1111";
M <= '0';
wait for 50 ns;
Sel <= "00-";
wait for 50 ns;
Sel <= "01-";
wait for 50 ns;
Sel <= "10-";
wait for 50 ns;
Sel <= "11-";
wait for 50 ns;
M <= '1';
Sel <= "000";
wait for 50 ns;
Sel <= "001";
wait for 50 ns;
Sel <= "010";
wait for 50 ns;
Sel <= "011";
wait for 50 ns;
Sel <= "100";
wait for 50 ns;
Sel <= "101";
wait for 50 ns;
Sel <= "110";
wait for 50 ns;
Sel <= "111";
-- insert stimulus here
wait;
end process;
END;][1]
您尝试使用 X 和 Y（以及您注释掉的内容）进行的操作是一种非常合理的连接 select 的方法。问题是不在乎。普通的 case 语句不会按照您期望的方式处理无关紧要的事情（即它不匹配它们，就好像它们可以是任何东西一样 - 它将它们作为唯一的 std_logic 值处理和其他一切一样）。如果您有支持 VHDL-2008 的工具，您可以使用 case?，它 确实 以您想要的方式匹配无关值。您甚至可以将 M 连接到您的 select 中，并稍微缩短您的代码。喜欢：
process (all)
variable sel : std_logic_vector(3 downto 0);
begin
sel := M & S1 & S0 & Cin;
case? sel is
when "000-" =>
Fx := A and B;
when "001-" =>
Fx := A or B;
...
when "1000" =>
...
（请注意，我在这里使用 sel 作为内部变量而不是端口。）
如果您不能使用 VHDL-2008，则必须适当地嵌套您的 if/case 语句。提示：你可以在 case 语句中使用 sel 的一部分，所以如果 Cin 总是不关心 M = '0'，你可以这样做：
process (M, S0, S1, Cin, A, B)
variable sel : std_logic_vector(2 downto 0);
begin
sel := S1 & S0 & Cin;
if M = '0' then
case sel(2 downto 1) is -- Cin is don't-care
when "00" =>
Fx := A and B;
when "01" =>
Fx := A or B;
...
else
case sel is -- all control bits are significant
when "000" =>
...
正如 Paebbels 所指出的，对您来说更好的解决方案可能只是在不关心的地方显式地提供多个选择，尽管对于具有更多控制位的设计来说这可能会变得乏味。
所以我一直在做这个作业，它要求我设计一个由几个位（即 S1、S0、Cin/C0（进位）和 M）控制的 4 位 ALU，具体取决于ALU 将根据 M 的值执行逻辑或算术运算。我临时设计了一个 ALU，它使用名为 'Sel' 的输入，同时我弄清楚如何获取 3 个差异输入（S0、S1、Cin/C0）的值。我不知道如何连接这 3 位。在执行逻辑运算时，我还使用“-”表示无关位。此外，由于我没有使用 3 个控制选择，所以模式 (m) 感觉是多余的。因此请忽略部分代码，因为它们没有用。
我在最后附上了一张图片，解释了预期的内容。
代码
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity codeALU is
Port ( A : in STD_LOGIC_VECTOR (3 downto 0);
B : in STD_LOGIC_VECTOR (3 downto 0);
Cin : in STD_LOGIC;
--S0 : in STD_LOGIC;
--S1 : in STD_LOGIC;
Sel : in STD_LOGIC_VECTOR (2 downto 0);
M : in STD_LOGIC;
Cout : out STD_LOGIC;
Z : out STD_LOGIC;
F : out STD_LOGIC_VECTOR (3 downto 0));
end codeALU;
architecture Behavioral of codeALU is
begin
process(A, B, M, Cin, Sel)
--variable X : STD_LOGIC_VECTOR (1 downto 0);
--variable Y : STD_LOGIC_VECTOR (2 downto 0);
variable temp : STD_LOGIC_VECTOR (4 downto 0);
variable Fx : STD_LOGIC_VECTOR (3 downto 0);
variable Cx, Zx : STD_LOGIC;
begin
--X := S1 & S0;
--Y := S1 & S0 & Cin;
Cx := '0';
Zx := '0';
if M = '0' then
Z <= '0';
case Sel is
when "00-" =>
Fx := A AND B;
Zx := '0';
when "01-" =>
Fx := A XOR B;
when "10-" =>
Fx := A OR B;
when "11-" =>
Fx := A XNOR B;
when others =>
null;
end case;
elsif M = '1' then
case Sel is
when "000" =>
temp := (B(3)&B(3 downto 1) + ('0'&A));
Fx := temp(3 downto 0);
Cx := temp(4);
when "001" =>
temp := (A(3)&A(3 downto 1) + ('0'&B));
Fx := temp(3 downto 0);
Cx := temp(4);
when "010" =>
temp := ('0'&A) + ('0'&B);
Fx := temp(3 downto 0);
Cx := temp(4);
when "011" =>
temp := ('0'&A) + ('0'&B) + ('0'&Cin);
Fx := temp(3 downto 0);
Cx := temp(4);
when "100" =>
temp := ('0'&A) + (not B);
Fx := temp(3 downto 0);
Cx := temp(4);
when "101" =>
temp := (not B) + ('0'&A) + 1;
Fx := temp(3 downto 0);
Cx := temp(4);
when "110" =>
temp := ('0'&A) + ('0'&B(3 downto 1));
Fx := temp(3 downto 0);
Cx := temp(4);
when "111" =>
temp := ('0'&B) + ('0'&A(3 downto 1));
Fx := temp(3 downto 0);
Cx := temp(4);
when others =>
null;
end case;
for i in 0 to 3 loop
Zx := Zx or Fx(i);
end loop;
Z <= not Zx;
else null;
end if;
F <= Fx;
Cout <= Cx;
end process;
end Behavioral;
测试台
![LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY test2ALU IS
END test2ALU;
ARCHITECTURE behavior OF test2ALU IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT codeALU
PORT(
A : IN std_logic_vector(3 downto 0);
B : IN std_logic_vector(3 downto 0);
Cin : IN std_logic;
Sel : IN std_logic_vector(2 downto 0);
M : IN std_logic;
Cout : OUT std_logic;
Z : OUT std_logic;
F : OUT std_logic_vector(3 downto 0)
);
END COMPONENT;
--Inputs
signal A : std_logic_vector(3 downto 0) := (others => '0');
signal B : std_logic_vector(3 downto 0) := (others => '0');
signal Cin : std_logic := '0';
signal Sel : std_logic_vector(2 downto 0) := (others => '0');
signal M : std_logic := '0';
--Outputs
signal Cout : std_logic;
signal Z : std_logic;
signal F : std_logic_vector(3 downto 0);
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: codeALU PORT MAP (
A => A,
B => B,
Cin => Cin,
Sel => Sel,
M => M,
Cout => Cout,
Z => Z,
F => F
);
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
A <= "1001";
B <= "1111";
M <= '0';
wait for 50 ns;
Sel <= "00-";
wait for 50 ns;
Sel <= "01-";
wait for 50 ns;
Sel <= "10-";
wait for 50 ns;
Sel <= "11-";
wait for 50 ns;
M <= '1';
Sel <= "000";
wait for 50 ns;
Sel <= "001";
wait for 50 ns;
Sel <= "010";
wait for 50 ns;
Sel <= "011";
wait for 50 ns;
Sel <= "100";
wait for 50 ns;
Sel <= "101";
wait for 50 ns;
Sel <= "110";
wait for 50 ns;
Sel <= "111";
-- insert stimulus here
wait;
end process;
END;][1]
您尝试使用 X 和 Y（以及您注释掉的内容）进行的操作是一种非常合理的连接 select 的方法。问题是不在乎。普通的 case 语句不会按照您期望的方式处理无关紧要的事情（即它不匹配它们，就好像它们可以是任何东西一样 - 它将它们作为唯一的 std_logic 值处理和其他一切一样）。如果您有支持 VHDL-2008 的工具，您可以使用 case?，它 确实 以您想要的方式匹配无关值。您甚至可以将 M 连接到您的 select 中，并稍微缩短您的代码。喜欢：
process (all)
variable sel : std_logic_vector(3 downto 0);
begin
sel := M & S1 & S0 & Cin;
case? sel is
when "000-" =>
Fx := A and B;
when "001-" =>
Fx := A or B;
...
when "1000" =>
...
（请注意，我在这里使用 sel 作为内部变量而不是端口。）
如果您不能使用 VHDL-2008，则必须适当地嵌套您的 if/case 语句。提示：你可以在 case 语句中使用 sel 的一部分，所以如果 Cin 总是不关心 M = '0'，你可以这样做：
process (M, S0, S1, Cin, A, B)
variable sel : std_logic_vector(2 downto 0);
begin
sel := S1 & S0 & Cin;
if M = '0' then
case sel(2 downto 1) is -- Cin is don't-care
when "00" =>
Fx := A and B;
when "01" =>
Fx := A or B;
...
else
case sel is -- all control bits are significant
when "000" =>
...
正如 Paebbels 所指出的，对您来说更好的解决方案可能只是在不关心的地方显式地提供多个选择，尽管对于具有更多控制位的设计来说这可能会变得乏味。