使用 ise 的 verilog 检查语法
verilog check syntax with ise
我写了一个模块，正在尝试检查语法。 ISE 输出给我这些错误
ERROR:HDLCompilers:26 - "../cmd_parser.v" line 220 unexpected token: '['
ERROR:HDLCompilers:26 - "../cmd_parser.v" line 221 unexpected token: '['
ERROR:HDLCompilers:26 - "../cmd_parser.v" line 222 unexpected token: '['
ERROR:HDLCompilers:26 - "../cmd_parser.v" line 225 unexpected token: '['
ERROR:HDLCompilers:26 - "../cmd_parser.v" line 226 unexpected token: '['
ERROR:HDLCompilers:26 - "../cmd_parser.v" line 228 unexpected token: '['
ERROR:HDLCompilers:26 - "../cmd_parser.v" line 230 unexpected token: '['
ERROR:HDLCompilers:26 - "../cmd_parser.v" line 245 unexpected token: 'reg'
ERROR:HDLCompilers:26 - "../cmd_parser.v" line 246 unexpected token: 'reg'
ERROR:HDLCompilers:26 - "../cmd_parser.v" line 247 unexpected token: 'reg'
ERROR:HDLCompilers:26 - "../cmd_parser.v" line 248 unexpected token: 'reg'
ERROR:HDLCompilers:26 - "../cmd_parser.v" line 249 unexpected token: 'reg'
ERROR:HDLCompilers:26 - "../cmd_parser.v" line 250 unexpected token: 'reg'
ERROR:HDLCompilers:26 - "../cmd_parser.v" line 251 unexpected token: 'reg'
ERROR:HDLCompilers:26 - "../cmd_parser.v" line 252 unexpected token: 'reg'
ERROR:HDLCompilers:26 - "../cmd_parser.v" line 253 unexpected token: 'reg'
ERROR:HDLCompilers:26 - "../cmd_parser.v" line 254 unexpected token: 'reg'
ERROR:HDLCompilers:26 - "../cmd_parser.v" line 255 unexpected token: 'reg'
ERROR:HDLCompilers:28 - "../cmd_parser.v" line 605 'reg32_23_DoppBoundaryLen' has not been declared
ERROR:HDLCompilers:28 - "../cmd_parser.v" line 652 'reg36_RangeSincCoef' has not been declared
ERROR:HDLCompilers:28 - "../cmd_parser.v" line 655 'reg36_2ndRangeSincCoef' has not been declared
ERROR:HDLCompilers:28 - "../cmd_parser.v" line 658 'reg36_3rdRangeSincCoef' has not been declared
ERROR:HDLCompilers:28 - "../cmd_parser.v" line 672 'reg37_PreSumSincCoef' has not been declared
ERROR:HDLCompilers:28 - "../cmd_parser.v" line 675 'reg37_2ndPreSumSincCoef' has not been declared
ERROR:HDLCompilers:28 - "../cmd_parser.v" line 678 'reg37_2ndPreSumSincCoef' has not been declared
ERROR:HDLCompilers:28 - "../cmd_parser.v" line 691 'reg38_1_sADCReg' has not been declared
ERROR:HDLCompilers:28 - "../cmd_parser.v" line 703 'TLM_CMD_HEADER' has not been declared
ERROR:HDLCompilers:28 - "../cmd_parser.v" line 710 'TLM_CDU' has not been declared
ERROR:HDLCompilers:28 - "../cmd_parser.v" line 711 'tlm1_CDU' has not been declared
ERROR:HDLCompilers:28 - "../cmd_parser.v" line 712 'tlm1_CDU' has not been declared
ERROR:HDLCompilers:28 - "../cmd_parser.v" line 717 'TLM_CD_SADC' has not been declared
ERROR:HDLCompilers:28 - "../cmd_parser.v" line 718 'tlm2_CD_sadc' has not been declared
ERROR:HDLCompilers:28 - "../cmd_parser.v" line 719 'tlm2_CD_sadc' has not been declared
ERROR:HDLCompilers:28 - "../cmd_parser.v" line 724 'TLM_ADC_1V' has not been declared
ERROR:HDLCompilers:28 - "../cmd_parser.v" line 725 'tlm3_adc1V' has not been declared
ERROR:HDLCompilers:28 - "../cmd_parser.v" line 726 'tlm3_adc1V' has not been declared
ERROR:HDLCompilers:28 - "../cmd_parser.v" line 731 'TLM_ADC_2V' has not been declared
ERROR:HDLCompilers:28 - "../cmd_parser.v" line 732 'tlm4_adc2V' has not been declared
ERROR:HDLCompilers:28 - "../cmd_parser.v" line 733 'tlm4_adc2V' has not been declared
ERROR:HDLCompilers:28 - "../cmd_parser.v" line 738 'TLM_ADC_3V' has not been declared
ERROR:HDLCompilers:28 - "../cmd_parser.v" line 739 'tlm5_adc3V' has not been declared
ERROR:HDLCompilers:28 - "../cmd_parser.v" line 740 'tlm5_adc3V' has not been declared
ERROR:HDLCompilers:28 - "../cmd_parser.v" line 745 'TLM_ADC_4V' has not been declared
ERROR:HDLCompilers:28 - "../cmd_parser.v" line 746 'tlm6_adc4V' has not been declared
ERROR:HDLCompilers:28 - "../cmd_parser.v" line 747 'tlm6_adc4V' has not been declared
ERROR:HDLCompilers:28 - "../cmd_parser.v" line 752 'TLM_ADC_DIE_TEMPS' has not been declared
ERROR:HDLCompilers:28 - "../cmd_parser.v" line 753 'tlm7_adcdietemp' has not been declared
ERROR:HDLCompilers:28 - "../cmd_parser.v" line 754 'tlm7_adcdietemp' has not been declared
ERROR:HDLCompilers:28 - "../cmd_parser.v" line 759 'TLM_STATUS_1' has not been declared
ERROR:HDLCompilers:28 - "../cmd_parser.v" line 760 'tlm8_status1' has not been declared
ERROR:HDLCompilers:28 - "../cmd_parser.v" line 761 'tlm8_status1' has not been declared
ERROR:HDLCompilers:28 - "../cmd_parser.v" line 766 'TLM_STATUS_2' has not been declared
ERROR:HDLCompilers:28 - "../cmd_parser.v" line 767 'tlm8_status2' has not been declared
ERROR:HDLCompilers:28 - "../cmd_parser.v" line 768 'tlm8_status2' has not been declared
ERROR:HDLCompilers:28 - "../cmd_parser.v" line 773 'TLM_STATUS_3' has not been declared
ERROR:HDLCompilers:28 - "../cmd_parser.v" line 774 'tlm8_status3' has not been declared
ERROR:HDLCompilers:28 - "../cmd_parser.v" line 775 'tlm8_status3' has not been declared
ERROR:HDLCompilers:28 - "../cmd_parser.v" line 780 'TLM_STATUS_4' has not been declared
ERROR:HDLCompilers:28 - "../cmd_parser.v" line 781 'tlm8_status4' has not been declared
ERROR:HDLCompilers:28 - "../cmd_parser.v" line 782 'tlm8_status4' has not been declared
ERROR:HDLCompilers:28 - "../cmd_parser.v" line 783 'TLM_CHECKSUM' has not been declared
ERROR:HDLCompilers:28 - "../cmd_parser.v" line 795 'TLM_CHECKSUM' has not been declared
ERROR:HDLCompilers:28 - "../cmd_parser.v" line 813 'blkRam_address_40' has not been declared
ERROR:HDLCompilers:28 - "../cmd_parser.v" line 814 'CANNED_DATA' has not been declared
ERROR:HDLCompilers:28 - "../cmd_parser.v" line 820 'reg42_Qdopp' has not been declared
ERROR:HDLCompilers:28 - "../cmd_parser.v" line 829 'CANNED_DATA' has not been declared
ERROR:HDLCompilers:28 - "../cmd_parser.v" line 840 'blkRam_address_43' has not been declared
ERROR:HDLCompilers:28 - "../cmd_parser.v" line 841 'CANNED_DATA' has not been declared
ERROR:HDLCompilers:208 - "../cmd_parser.v" line 59 Port reference 'reg38_1_sADCReg' was not declared as input, inout or output
ERROR:HDLCompilers:208 - "../cmd_parser.v" line 73 Port reference 'tlm_data_out' was not declared as input, inout or output
ERROR:HDLCompilers:208 - "../cmd_parser.v" line 57 Port reference 'reg37_PreSumSincCoef' was not declared as input, inout or output
ERROR:HDLCompilers:208 - "../cmd_parser.v" line 54 Port reference 'reg36_2ndRangeSincCoef' was not declared as input, inout or output
ERROR:HDLCompilers:208 - "../cmd_parser.v" line 84 Port reference 'tlm7_adcdietemp' was not declared as input, inout or output
ERROR:HDLCompilers:208 - "../cmd_parser.v" line 78 Port reference 'tlm1_CDU' was not declared as input, inout or output
ERROR:HDLCompilers:208 - "../cmd_parser.v" line 53 Port reference 'reg36_RangeSincCoef' was not declared as input, inout or output
ERROR:HDLCompilers:208 - "../cmd_parser.v" line 85 Port reference 'tlm8_status1' was not declared as input, inout or output
ERROR:HDLCompilers:208 - "../cmd_parser.v" line 86 Port reference 'tlm8_status2' was not declared as input, inout or output
ERROR:HDLCompilers:208 - "../cmd_parser.v" line 87 Port reference 'tlm8_status3' was not declared as input, inout or output
ERROR:HDLCompilers:208 - "../cmd_parser.v" line 88 Port reference 'tlm8_status4' was not declared as input, inout or output
ERROR:HDLCompilers:208 - "../cmd_parser.v" line 58 Port reference 'reg37_2ndPreSumSincCoef' was not declared as input, inout or output
ERROR:HDLCompilers:208 - "../cmd_parser.v" line 55 Port reference 'reg36_3rdRangeSincCoef' was not declared as input, inout or output
ERROR:HDLCompilers:208 - "../cmd_parser.v" line 61 Port reference 'reg42_Qdopp' was not declared as input, inout or output
ERROR:HDLCompilers:208 - "../cmd_parser.v" line 83 Port reference 'tlm6_adc4V' was not declared as input, inout or output
ERROR:HDLCompilers:208 - "../cmd_parser.v" line 79 Port reference 'tlm2_CD_sadc' was not declared as input, inout or output
ERROR:HDLCompilers:208 - "../cmd_parser.v" line 82 Port reference 'tlm5_adc3V' was not declared as input, inout or output
ERROR:HDLCompilers:208 - "../cmd_parser.v" line 81 Port reference 'tlm4_adc2V' was not declared as input, inout or output
ERROR:HDLCompilers:208 - "../cmd_parser.v" line 80 Port reference 'tlm3_adc1V' was not declared as input, inout or output
这是我的代码：
模块 CmdParser(
// control signals
clk,
rst,
// output registers
reg32_1_misc,
reg32_10_EIF,
reg32_12_ILineLen,
reg32_13_RCOutLen,
reg32_14_CalAvgLen,
reg32_15_CalWinLen,
reg32_16_CalWinStart,
reg32_18_RcvOnlyNoiseWinLen,
reg32_19_RcvOnlyNoiseWinStart,
reg32_20_BoundaryLen,
reg32_21_RawWinLen,
reg32_22_CduRfuDelays,
reg33_2_DataFlow,
reg33_3_PulseCntSync,
reg34_1_OceanDWP,
reg34_2_LandDWP,
reg35_1_LandDriftRate,
reg35_2_LandWinLen,
reg36_1_Range,
reg36_RangeSincCoef,
reg36_2ndRangeSincCoef,
reg36_3rdRangeSincCoef,
reg37_1_PreSum,
reg37_PreSumSincCoef,
reg37_2ndPreSumSincCoef,
reg38_1_sADCReg,
blkRam_40_address,
reg42_Qdopp,
blkRam_43_address,
reg48_DopAziCoef,
reg49_DopRanCoef,
reg50_DopplerIndx,
reg50_DopplerWze,
reg50_DopplerOfft,
reg51_Dopp_Bs,
reg51_NumOfPolynomials,
reg51_PolyCoefficients,
reg51_QdoppData,
tlm_data_out,
tlm_ctu_rdy,
// input registers
tlm_ctu_rdy,
tlm1_CDU,
tlm2_CD_sadc,
tlm3_adc1V,
tlm4_adc2V,
tlm5_adc3V,
tlm6_adc4V,
tlm7_adcdietemp,
tlm8_status1,
tlm8_status2,
tlm8_status3,
tlm8_status4,
data_in_sw,
blkRam_40_dout,
blkRam_43_dout,
cmd_read_rdy,
cmd_good_counter, //CMD is good if sync_code is = 0'hC9
sync_code_error,
sync_code_error_counter,
past_TRF_count_error,
transmit_pulse_count_error, //Error counter when the specified TRF has already occurred
parameter_id_error,
dma_data_out_tlm,
checksum_error,
parameter_id
);
parameter RAM_ADDR_BITS = `RAM_ADDR_BITS;
parameter RAM_WIDTH = `RAM_WIDTH;
parameter ALMOST_FULL_THRESHOLD = `ALMOST_FULL_THRESHOLD;
parameter ALMOST_EMPTY_THRESHOLD = `ALMOST_EMPTY_THRESHOLD;
//State machine encoding
parameter CMD_HEADER = 1;
parameter CHECK_SYNC_CODE = 2;
parameter TRANSMIT_PULSE = 3;
parameter TPC_WAIT = 4;
parameter PACKET_LENGTH = 5;
parameter N_DATA = 6;
parameter CHECKSUM = 7;
parameter VERIFY_CHECKSUM = 8;
parameter N_REG38 = 5;
parameter N_REG40 = 8192;
parameter N_REG42 = 16;
parameter N_REG43 = 16;
parameter N_REG44 = 4;
parameter CLK_DIV = 5;
parameter NUM_SUB_ASSEMBLIES = 11;
parameter CTU = 0;
parameter TLM = 1;
parameter HOBSP = 2;
parameter VOBSP = 3;
parameter NOBSP = 4;
parameter SSRI = 5;
parameter YSPP_BOTH = 6;
parameter YSPP_FPGA_1 = 7; //+YSPP
parameter YSPP_FPGA_2 = 8; //-YSPP
parameter NSPP = 9;
parameter RFU = 10;
parameter SPP_STATIC_REGISTERS = 32;
parameter SPP_CONTROL_REGISTERS = 33;
parameter DWP = 34;
parameter DWP_DRIFT = 35;
parameter LAND_PROCESSING_RANGE_SINC = 36;
parameter LAND_PROCESSING_AZIMUTH_SINC = 37;
parameter SADC_PROGRAMMING = 38;
parameter TELEMETRY = 39;
parameter LOOPBACK_RC_CORRECTION = 40;
parameter DOPPLER_QDOOP = 42;
parameter DOPPLER_AZIMUTH_COEFFICIENTS = 48;
parameter DOPPLER_RANGE_COEFFICIENTS = 49;
parameter DOPPLER_RANGE_INDEXES = 50;
// Inputs
input clk; //Main FPGA clk
input rst;
// jWire rx signals
input data_in_sw;
reg [31:0] jWire_data_in;
reg jWire_val_data_in;
// input fifo signals
reg ififo_read_enable;
reg [31:0] cmd_data_fifo_in;
reg ififo_empty;
reg ififo_full;
reg ififo_almost_full;
reg iififo_empty;
// output fifo signals
reg jWire_write_enable;
reg ofifo_read_enable;
reg ofifo_empty;
reg ofifo_full;
reg ofifo_almost_full;
reg oififo_empty;
// jWire tx signals
reg [31:0] tlm_data_fifo_out;
reg tlm_data_sw;
reg tlm_sync_sw;
reg tlm_busy_sw;
reg [31:0] blkRam_40_din;
output reg [31:0] blkRam_40_dout;
output reg blkRam_40_address;
reg [31:0] blkRam_43_din;
output reg [31:0] blkRam_43_dout;
output reg blkRam_43_address;
output reg cmd_read_rdy;
reg register_number;
//-------------------------------------------------------------------------//
output reg [31:0]reg32_1_misc; //[25'd0,CannedRRF,CrossPol,AcqEn,4'd0]
output reg [31:0]reg32_10_EIF; //[25'd0,IEF[6:0]]
output reg [31:0]reg32_12_ILineLen; //[19'd0,ILineLen[12:0]], default: YSPP 8192, NSPP 4096
output reg [31:0]reg32_13_RCOutLen; //[19'd0,RCOutLen[12:0]], default: 5820
output reg [31:0]reg32_14_CalAvgLen; //[19'd0,CalAvgLen[12:0]], default: 6840
output reg [31:0]reg32_15_CalWinLen; //[19'd0,CalWinLen[12:0]], default: 2700
output reg [31:0]reg32_16_CalWinStart; //[CalWinStart[31:16],LBWinStart[15:0]], default: 3398 (300mhz),1196 (300mhz)
output reg [31:0]reg32_18_RcvOnlyNoiseWinLen; //[19'd0,RcvOnlyNoiseWinLen[12:0]], default: TBD
output reg [31:0]reg32_19_RcvOnlyNoiseWinStart; //[16'd0,RcvOnlyNoiseWinStart[15:0]], default:5570
output reg [31:0]reg32_20_BoundaryLen; //[AvgBoundLen[31:16],PixelBoundLen[15:0]] default: 6840,1368
output reg [31:0]reg32_21_RawWinLen;//[18'd0,RawWinLen[13:0]], default: 8192 YSPP, 4096 NSPP
output reg [31:0]reg32_22_CduRfuDelays; //[12'd0,RfuSyncDelay[19:10],RfuTrfDelay[9:0]], default:
output reg [31:0]reg32_23_DoppBoundaryLen;
output reg [31:0]reg33_2_DataFlow; //[CannedDataLines[31:16],11'd0,CannedDataRun,CannedDataEnable,
// RawDataRun,LandDataRun,OceanDataRun]
output reg [31:0]reg33_3_PulseCntSync; //[TR_Pulse_cnt[31:0]]
output reg [31:0]reg34_1_OceanDWP; //[16'd0,OceanDWP[15:0]]
output reg [31:0]reg34_2_LandDWP; //[DQPH/DWP_left_norm/DWP_right_flip[31:0],DWPV/DWP_right_norm/DWP_left_flip[15:0]]
//reg [31:0] reg34_3_LandRawDWL; // Gone?
output reg [31:0]reg35_1_LandDriftRate; //[24'd0,DWPdrift[7:0]]
output reg [31:0]reg35_2_LandWinLen; //[16'd0,WinLen[15:0]]
output reg [31:0]reg36_1_Range; //[11'd0,RangeFiltLen[12:8],3'd0,RangeDecFac[4:0]], default: 2
output reg [31:0] reg36_RangeSincCoef [0:15]; // default: 0's
output reg [31:0]reg36_2ndRangeSincCoef[0:15]; // default: 0's
output reg [31:0]reg36_3rdRangeSincCoef[0:15]; // default: 0's
output reg [31:0]reg37_1_PreSum;//[11'd0,PresumFiltLen[12:8],3'd0,PresumDecFac[4:0]], default: 2
output reg [31:0]reg37_PreSumSincCoef[0:15]; // default: 0's
output reg [31:0]reg37_2ndPreSumSincCoef[0:15]; // default: 0's
output reg [31:0]reg38_1_sADCReg[0:N_REG38]; //[3rdReg[31:24],2ndReg[23:16],1stReg[15:8],ADCSel,ByteCnt[6:5],Addr[4:0]], default: x, x, x, Q=0, I=1, x, x
output reg [31:0]reg42_Qdopp[0:N_REG42];
output reg [31:0]reg48_DopAziCoef;
output reg [31:0]reg49_DopRanCoef;
output reg [31:0]reg50_DopplerIndx;
output reg [31:0]reg50_DopplerWze;
output reg [31:0]reg50_DopplerOfft;
output reg [31:0]reg51_Dopp_Bs;
output reg [31:0]reg51_NumOfPolynomials;
output reg [31:0]reg51_PolyCoefficients;
output reg [31:0]reg51_QdoppData;
input reg [31:0] tlm1_CDU;
input reg [31:0] tlm2_CD_sadc;
input reg [31:0] tlm3_adc1V;
input reg [31:0] tlm4_adc2V;
input reg [31:0] tlm5_adc3V;
input reg [31:0] tlm6_adc4V;
input reg [31:0] tlm7_adcdietemp;
input reg [31:0] tlm8_status1;
input reg [31:0] tlm8_status2;
input reg [31:0] tlm8_status3;
input reg [31:0] tlm8_status4;
//Telemetry
output reg [31:0] cmd_good_counter; //CMD is good if sync_code is = 0'hC9
output reg sync_code_error;
output reg [31:0] sync_code_error_counter;
output reg [4:0] past_TRF_count_error;
output reg [31:0] transmit_pulse_count_error; //Error counter when the specified TRF has already occurred
output reg [31:0] parameter_id_error;
output reg [31:0] dma_data_out_tlm;
output reg [4:0] checksum_error;
//Internal signals: Packet parsing
reg [10:0] sequence_number;
reg [4:0] sub_assembly_id;
output reg [7:0] parameter_id;
reg [7:0] sync_code;
reg [31:0] transmit_pulse_count;
reg [31:0] transmit_pulse_count_prior;
reg [15:0] length_of_packet;
reg spp_control_count;
//Watchdog timer
//Starts 32 bit counter when first word has been received (i.e. FIFO is not empty)
//Counter will run until checksum has been parsed and transmitted
//If watchdog counter fills up before the DMA CMD Route state machine has completed then watchdog_error_counter will be incremented
reg [31:0] watchdog_timeout;
reg watchdog_timer;
reg [4:0] watchdog_error_counter;
reg purge_cmd; //Flag to dump DMA data until next valid command comes through
reg [31:0] packet_num_count;
reg [31:0] cmd_header_packet;
reg [4:0] parse_state;
reg [31:0] data_packet;
reg wait_counter;
// Checksum registers
reg crcfd;
reg crcnd;
reg crcrdy;
reg [31:0] crcDin;
reg [31:0] crcDout;
reg [15:0] computed_checksum;
wire [15:0] com_checksum;
reg [15:0] transmited_checksum;
assign computed_checksum = com_checksum;
// TLM Checksum registers
output reg tlm_ctu_rdy;
reg tlmfd;
reg tlmnd;
reg tlmrdy;
reg [31:0] tlmDin;
reg [31:0] tlmDout;
reg [15:0] tlm_computed_checksum;
wire [15:0] tlm_com_checksum;
任何建议都会有所帮助。我已经检查过，似乎寄存器数组有问题。
谢谢
所以问题是您不允许使用 reg 数组分配端口。这在 SystemVerilog 和 VHDL 中是允许的，但在 verilog 中是不允许的。
我写了一个模块，正在尝试检查语法。 ISE 输出给我这些错误
ERROR:HDLCompilers:26 - "../cmd_parser.v" line 220 unexpected token: '['
ERROR:HDLCompilers:26 - "../cmd_parser.v" line 221 unexpected token: '['
ERROR:HDLCompilers:26 - "../cmd_parser.v" line 222 unexpected token: '['
ERROR:HDLCompilers:26 - "../cmd_parser.v" line 225 unexpected token: '['
ERROR:HDLCompilers:26 - "../cmd_parser.v" line 226 unexpected token: '['
ERROR:HDLCompilers:26 - "../cmd_parser.v" line 228 unexpected token: '['
ERROR:HDLCompilers:26 - "../cmd_parser.v" line 230 unexpected token: '['
ERROR:HDLCompilers:26 - "../cmd_parser.v" line 245 unexpected token: 'reg'
ERROR:HDLCompilers:26 - "../cmd_parser.v" line 246 unexpected token: 'reg'
ERROR:HDLCompilers:26 - "../cmd_parser.v" line 247 unexpected token: 'reg'
ERROR:HDLCompilers:26 - "../cmd_parser.v" line 248 unexpected token: 'reg'
ERROR:HDLCompilers:26 - "../cmd_parser.v" line 249 unexpected token: 'reg'
ERROR:HDLCompilers:26 - "../cmd_parser.v" line 250 unexpected token: 'reg'
ERROR:HDLCompilers:26 - "../cmd_parser.v" line 251 unexpected token: 'reg'
ERROR:HDLCompilers:26 - "../cmd_parser.v" line 252 unexpected token: 'reg'
ERROR:HDLCompilers:26 - "../cmd_parser.v" line 253 unexpected token: 'reg'
ERROR:HDLCompilers:26 - "../cmd_parser.v" line 254 unexpected token: 'reg'
ERROR:HDLCompilers:26 - "../cmd_parser.v" line 255 unexpected token: 'reg'
ERROR:HDLCompilers:28 - "../cmd_parser.v" line 605 'reg32_23_DoppBoundaryLen' has not been declared
ERROR:HDLCompilers:28 - "../cmd_parser.v" line 652 'reg36_RangeSincCoef' has not been declared
ERROR:HDLCompilers:28 - "../cmd_parser.v" line 655 'reg36_2ndRangeSincCoef' has not been declared
ERROR:HDLCompilers:28 - "../cmd_parser.v" line 658 'reg36_3rdRangeSincCoef' has not been declared
ERROR:HDLCompilers:28 - "../cmd_parser.v" line 672 'reg37_PreSumSincCoef' has not been declared
ERROR:HDLCompilers:28 - "../cmd_parser.v" line 675 'reg37_2ndPreSumSincCoef' has not been declared
ERROR:HDLCompilers:28 - "../cmd_parser.v" line 678 'reg37_2ndPreSumSincCoef' has not been declared
ERROR:HDLCompilers:28 - "../cmd_parser.v" line 691 'reg38_1_sADCReg' has not been declared
ERROR:HDLCompilers:28 - "../cmd_parser.v" line 703 'TLM_CMD_HEADER' has not been declared
ERROR:HDLCompilers:28 - "../cmd_parser.v" line 710 'TLM_CDU' has not been declared
ERROR:HDLCompilers:28 - "../cmd_parser.v" line 711 'tlm1_CDU' has not been declared
ERROR:HDLCompilers:28 - "../cmd_parser.v" line 712 'tlm1_CDU' has not been declared
ERROR:HDLCompilers:28 - "../cmd_parser.v" line 717 'TLM_CD_SADC' has not been declared
ERROR:HDLCompilers:28 - "../cmd_parser.v" line 718 'tlm2_CD_sadc' has not been declared
ERROR:HDLCompilers:28 - "../cmd_parser.v" line 719 'tlm2_CD_sadc' has not been declared
ERROR:HDLCompilers:28 - "../cmd_parser.v" line 724 'TLM_ADC_1V' has not been declared
ERROR:HDLCompilers:28 - "../cmd_parser.v" line 725 'tlm3_adc1V' has not been declared
ERROR:HDLCompilers:28 - "../cmd_parser.v" line 726 'tlm3_adc1V' has not been declared
ERROR:HDLCompilers:28 - "../cmd_parser.v" line 731 'TLM_ADC_2V' has not been declared
ERROR:HDLCompilers:28 - "../cmd_parser.v" line 732 'tlm4_adc2V' has not been declared
ERROR:HDLCompilers:28 - "../cmd_parser.v" line 733 'tlm4_adc2V' has not been declared
ERROR:HDLCompilers:28 - "../cmd_parser.v" line 738 'TLM_ADC_3V' has not been declared
ERROR:HDLCompilers:28 - "../cmd_parser.v" line 739 'tlm5_adc3V' has not been declared
ERROR:HDLCompilers:28 - "../cmd_parser.v" line 740 'tlm5_adc3V' has not been declared
ERROR:HDLCompilers:28 - "../cmd_parser.v" line 745 'TLM_ADC_4V' has not been declared
ERROR:HDLCompilers:28 - "../cmd_parser.v" line 746 'tlm6_adc4V' has not been declared
ERROR:HDLCompilers:28 - "../cmd_parser.v" line 747 'tlm6_adc4V' has not been declared
ERROR:HDLCompilers:28 - "../cmd_parser.v" line 752 'TLM_ADC_DIE_TEMPS' has not been declared
ERROR:HDLCompilers:28 - "../cmd_parser.v" line 753 'tlm7_adcdietemp' has not been declared
ERROR:HDLCompilers:28 - "../cmd_parser.v" line 754 'tlm7_adcdietemp' has not been declared
ERROR:HDLCompilers:28 - "../cmd_parser.v" line 759 'TLM_STATUS_1' has not been declared
ERROR:HDLCompilers:28 - "../cmd_parser.v" line 760 'tlm8_status1' has not been declared
ERROR:HDLCompilers:28 - "../cmd_parser.v" line 761 'tlm8_status1' has not been declared
ERROR:HDLCompilers:28 - "../cmd_parser.v" line 766 'TLM_STATUS_2' has not been declared
ERROR:HDLCompilers:28 - "../cmd_parser.v" line 767 'tlm8_status2' has not been declared
ERROR:HDLCompilers:28 - "../cmd_parser.v" line 768 'tlm8_status2' has not been declared
ERROR:HDLCompilers:28 - "../cmd_parser.v" line 773 'TLM_STATUS_3' has not been declared
ERROR:HDLCompilers:28 - "../cmd_parser.v" line 774 'tlm8_status3' has not been declared
ERROR:HDLCompilers:28 - "../cmd_parser.v" line 775 'tlm8_status3' has not been declared
ERROR:HDLCompilers:28 - "../cmd_parser.v" line 780 'TLM_STATUS_4' has not been declared
ERROR:HDLCompilers:28 - "../cmd_parser.v" line 781 'tlm8_status4' has not been declared
ERROR:HDLCompilers:28 - "../cmd_parser.v" line 782 'tlm8_status4' has not been declared
ERROR:HDLCompilers:28 - "../cmd_parser.v" line 783 'TLM_CHECKSUM' has not been declared
ERROR:HDLCompilers:28 - "../cmd_parser.v" line 795 'TLM_CHECKSUM' has not been declared
ERROR:HDLCompilers:28 - "../cmd_parser.v" line 813 'blkRam_address_40' has not been declared
ERROR:HDLCompilers:28 - "../cmd_parser.v" line 814 'CANNED_DATA' has not been declared
ERROR:HDLCompilers:28 - "../cmd_parser.v" line 820 'reg42_Qdopp' has not been declared
ERROR:HDLCompilers:28 - "../cmd_parser.v" line 829 'CANNED_DATA' has not been declared
ERROR:HDLCompilers:28 - "../cmd_parser.v" line 840 'blkRam_address_43' has not been declared
ERROR:HDLCompilers:28 - "../cmd_parser.v" line 841 'CANNED_DATA' has not been declared
ERROR:HDLCompilers:208 - "../cmd_parser.v" line 59 Port reference 'reg38_1_sADCReg' was not declared as input, inout or output
ERROR:HDLCompilers:208 - "../cmd_parser.v" line 73 Port reference 'tlm_data_out' was not declared as input, inout or output
ERROR:HDLCompilers:208 - "../cmd_parser.v" line 57 Port reference 'reg37_PreSumSincCoef' was not declared as input, inout or output
ERROR:HDLCompilers:208 - "../cmd_parser.v" line 54 Port reference 'reg36_2ndRangeSincCoef' was not declared as input, inout or output
ERROR:HDLCompilers:208 - "../cmd_parser.v" line 84 Port reference 'tlm7_adcdietemp' was not declared as input, inout or output
ERROR:HDLCompilers:208 - "../cmd_parser.v" line 78 Port reference 'tlm1_CDU' was not declared as input, inout or output
ERROR:HDLCompilers:208 - "../cmd_parser.v" line 53 Port reference 'reg36_RangeSincCoef' was not declared as input, inout or output
ERROR:HDLCompilers:208 - "../cmd_parser.v" line 85 Port reference 'tlm8_status1' was not declared as input, inout or output
ERROR:HDLCompilers:208 - "../cmd_parser.v" line 86 Port reference 'tlm8_status2' was not declared as input, inout or output
ERROR:HDLCompilers:208 - "../cmd_parser.v" line 87 Port reference 'tlm8_status3' was not declared as input, inout or output
ERROR:HDLCompilers:208 - "../cmd_parser.v" line 88 Port reference 'tlm8_status4' was not declared as input, inout or output
ERROR:HDLCompilers:208 - "../cmd_parser.v" line 58 Port reference 'reg37_2ndPreSumSincCoef' was not declared as input, inout or output
ERROR:HDLCompilers:208 - "../cmd_parser.v" line 55 Port reference 'reg36_3rdRangeSincCoef' was not declared as input, inout or output
ERROR:HDLCompilers:208 - "../cmd_parser.v" line 61 Port reference 'reg42_Qdopp' was not declared as input, inout or output
ERROR:HDLCompilers:208 - "../cmd_parser.v" line 83 Port reference 'tlm6_adc4V' was not declared as input, inout or output
ERROR:HDLCompilers:208 - "../cmd_parser.v" line 79 Port reference 'tlm2_CD_sadc' was not declared as input, inout or output
ERROR:HDLCompilers:208 - "../cmd_parser.v" line 82 Port reference 'tlm5_adc3V' was not declared as input, inout or output
ERROR:HDLCompilers:208 - "../cmd_parser.v" line 81 Port reference 'tlm4_adc2V' was not declared as input, inout or output
ERROR:HDLCompilers:208 - "../cmd_parser.v" line 80 Port reference 'tlm3_adc1V' was not declared as input, inout or output
这是我的代码：
模块 CmdParser(
// control signals
clk,
rst,
// output registers
reg32_1_misc,
reg32_10_EIF,
reg32_12_ILineLen,
reg32_13_RCOutLen,
reg32_14_CalAvgLen,
reg32_15_CalWinLen,
reg32_16_CalWinStart,
reg32_18_RcvOnlyNoiseWinLen,
reg32_19_RcvOnlyNoiseWinStart,
reg32_20_BoundaryLen,
reg32_21_RawWinLen,
reg32_22_CduRfuDelays,
reg33_2_DataFlow,
reg33_3_PulseCntSync,
reg34_1_OceanDWP,
reg34_2_LandDWP,
reg35_1_LandDriftRate,
reg35_2_LandWinLen,
reg36_1_Range,
reg36_RangeSincCoef,
reg36_2ndRangeSincCoef,
reg36_3rdRangeSincCoef,
reg37_1_PreSum,
reg37_PreSumSincCoef,
reg37_2ndPreSumSincCoef,
reg38_1_sADCReg,
blkRam_40_address,
reg42_Qdopp,
blkRam_43_address,
reg48_DopAziCoef,
reg49_DopRanCoef,
reg50_DopplerIndx,
reg50_DopplerWze,
reg50_DopplerOfft,
reg51_Dopp_Bs,
reg51_NumOfPolynomials,
reg51_PolyCoefficients,
reg51_QdoppData,
tlm_data_out,
tlm_ctu_rdy,
// input registers
tlm_ctu_rdy,
tlm1_CDU,
tlm2_CD_sadc,
tlm3_adc1V,
tlm4_adc2V,
tlm5_adc3V,
tlm6_adc4V,
tlm7_adcdietemp,
tlm8_status1,
tlm8_status2,
tlm8_status3,
tlm8_status4,
data_in_sw,
blkRam_40_dout,
blkRam_43_dout,
cmd_read_rdy,
cmd_good_counter, //CMD is good if sync_code is = 0'hC9
sync_code_error,
sync_code_error_counter,
past_TRF_count_error,
transmit_pulse_count_error, //Error counter when the specified TRF has already occurred
parameter_id_error,
dma_data_out_tlm,
checksum_error,
parameter_id
);
parameter RAM_ADDR_BITS = `RAM_ADDR_BITS;
parameter RAM_WIDTH = `RAM_WIDTH;
parameter ALMOST_FULL_THRESHOLD = `ALMOST_FULL_THRESHOLD;
parameter ALMOST_EMPTY_THRESHOLD = `ALMOST_EMPTY_THRESHOLD;
//State machine encoding
parameter CMD_HEADER = 1;
parameter CHECK_SYNC_CODE = 2;
parameter TRANSMIT_PULSE = 3;
parameter TPC_WAIT = 4;
parameter PACKET_LENGTH = 5;
parameter N_DATA = 6;
parameter CHECKSUM = 7;
parameter VERIFY_CHECKSUM = 8;
parameter N_REG38 = 5;
parameter N_REG40 = 8192;
parameter N_REG42 = 16;
parameter N_REG43 = 16;
parameter N_REG44 = 4;
parameter CLK_DIV = 5;
parameter NUM_SUB_ASSEMBLIES = 11;
parameter CTU = 0;
parameter TLM = 1;
parameter HOBSP = 2;
parameter VOBSP = 3;
parameter NOBSP = 4;
parameter SSRI = 5;
parameter YSPP_BOTH = 6;
parameter YSPP_FPGA_1 = 7; //+YSPP
parameter YSPP_FPGA_2 = 8; //-YSPP
parameter NSPP = 9;
parameter RFU = 10;
parameter SPP_STATIC_REGISTERS = 32;
parameter SPP_CONTROL_REGISTERS = 33;
parameter DWP = 34;
parameter DWP_DRIFT = 35;
parameter LAND_PROCESSING_RANGE_SINC = 36;
parameter LAND_PROCESSING_AZIMUTH_SINC = 37;
parameter SADC_PROGRAMMING = 38;
parameter TELEMETRY = 39;
parameter LOOPBACK_RC_CORRECTION = 40;
parameter DOPPLER_QDOOP = 42;
parameter DOPPLER_AZIMUTH_COEFFICIENTS = 48;
parameter DOPPLER_RANGE_COEFFICIENTS = 49;
parameter DOPPLER_RANGE_INDEXES = 50;
// Inputs
input clk; //Main FPGA clk
input rst;
// jWire rx signals
input data_in_sw;
reg [31:0] jWire_data_in;
reg jWire_val_data_in;
// input fifo signals
reg ififo_read_enable;
reg [31:0] cmd_data_fifo_in;
reg ififo_empty;
reg ififo_full;
reg ififo_almost_full;
reg iififo_empty;
// output fifo signals
reg jWire_write_enable;
reg ofifo_read_enable;
reg ofifo_empty;
reg ofifo_full;
reg ofifo_almost_full;
reg oififo_empty;
// jWire tx signals
reg [31:0] tlm_data_fifo_out;
reg tlm_data_sw;
reg tlm_sync_sw;
reg tlm_busy_sw;
reg [31:0] blkRam_40_din;
output reg [31:0] blkRam_40_dout;
output reg blkRam_40_address;
reg [31:0] blkRam_43_din;
output reg [31:0] blkRam_43_dout;
output reg blkRam_43_address;
output reg cmd_read_rdy;
reg register_number;
//-------------------------------------------------------------------------//
output reg [31:0]reg32_1_misc; //[25'd0,CannedRRF,CrossPol,AcqEn,4'd0]
output reg [31:0]reg32_10_EIF; //[25'd0,IEF[6:0]]
output reg [31:0]reg32_12_ILineLen; //[19'd0,ILineLen[12:0]], default: YSPP 8192, NSPP 4096
output reg [31:0]reg32_13_RCOutLen; //[19'd0,RCOutLen[12:0]], default: 5820
output reg [31:0]reg32_14_CalAvgLen; //[19'd0,CalAvgLen[12:0]], default: 6840
output reg [31:0]reg32_15_CalWinLen; //[19'd0,CalWinLen[12:0]], default: 2700
output reg [31:0]reg32_16_CalWinStart; //[CalWinStart[31:16],LBWinStart[15:0]], default: 3398 (300mhz),1196 (300mhz)
output reg [31:0]reg32_18_RcvOnlyNoiseWinLen; //[19'd0,RcvOnlyNoiseWinLen[12:0]], default: TBD
output reg [31:0]reg32_19_RcvOnlyNoiseWinStart; //[16'd0,RcvOnlyNoiseWinStart[15:0]], default:5570
output reg [31:0]reg32_20_BoundaryLen; //[AvgBoundLen[31:16],PixelBoundLen[15:0]] default: 6840,1368
output reg [31:0]reg32_21_RawWinLen;//[18'd0,RawWinLen[13:0]], default: 8192 YSPP, 4096 NSPP
output reg [31:0]reg32_22_CduRfuDelays; //[12'd0,RfuSyncDelay[19:10],RfuTrfDelay[9:0]], default:
output reg [31:0]reg32_23_DoppBoundaryLen;
output reg [31:0]reg33_2_DataFlow; //[CannedDataLines[31:16],11'd0,CannedDataRun,CannedDataEnable,
// RawDataRun,LandDataRun,OceanDataRun]
output reg [31:0]reg33_3_PulseCntSync; //[TR_Pulse_cnt[31:0]]
output reg [31:0]reg34_1_OceanDWP; //[16'd0,OceanDWP[15:0]]
output reg [31:0]reg34_2_LandDWP; //[DQPH/DWP_left_norm/DWP_right_flip[31:0],DWPV/DWP_right_norm/DWP_left_flip[15:0]]
//reg [31:0] reg34_3_LandRawDWL; // Gone?
output reg [31:0]reg35_1_LandDriftRate; //[24'd0,DWPdrift[7:0]]
output reg [31:0]reg35_2_LandWinLen; //[16'd0,WinLen[15:0]]
output reg [31:0]reg36_1_Range; //[11'd0,RangeFiltLen[12:8],3'd0,RangeDecFac[4:0]], default: 2
output reg [31:0] reg36_RangeSincCoef [0:15]; // default: 0's
output reg [31:0]reg36_2ndRangeSincCoef[0:15]; // default: 0's
output reg [31:0]reg36_3rdRangeSincCoef[0:15]; // default: 0's
output reg [31:0]reg37_1_PreSum;//[11'd0,PresumFiltLen[12:8],3'd0,PresumDecFac[4:0]], default: 2
output reg [31:0]reg37_PreSumSincCoef[0:15]; // default: 0's
output reg [31:0]reg37_2ndPreSumSincCoef[0:15]; // default: 0's
output reg [31:0]reg38_1_sADCReg[0:N_REG38]; //[3rdReg[31:24],2ndReg[23:16],1stReg[15:8],ADCSel,ByteCnt[6:5],Addr[4:0]], default: x, x, x, Q=0, I=1, x, x
output reg [31:0]reg42_Qdopp[0:N_REG42];
output reg [31:0]reg48_DopAziCoef;
output reg [31:0]reg49_DopRanCoef;
output reg [31:0]reg50_DopplerIndx;
output reg [31:0]reg50_DopplerWze;
output reg [31:0]reg50_DopplerOfft;
output reg [31:0]reg51_Dopp_Bs;
output reg [31:0]reg51_NumOfPolynomials;
output reg [31:0]reg51_PolyCoefficients;
output reg [31:0]reg51_QdoppData;
input reg [31:0] tlm1_CDU;
input reg [31:0] tlm2_CD_sadc;
input reg [31:0] tlm3_adc1V;
input reg [31:0] tlm4_adc2V;
input reg [31:0] tlm5_adc3V;
input reg [31:0] tlm6_adc4V;
input reg [31:0] tlm7_adcdietemp;
input reg [31:0] tlm8_status1;
input reg [31:0] tlm8_status2;
input reg [31:0] tlm8_status3;
input reg [31:0] tlm8_status4;
//Telemetry
output reg [31:0] cmd_good_counter; //CMD is good if sync_code is = 0'hC9
output reg sync_code_error;
output reg [31:0] sync_code_error_counter;
output reg [4:0] past_TRF_count_error;
output reg [31:0] transmit_pulse_count_error; //Error counter when the specified TRF has already occurred
output reg [31:0] parameter_id_error;
output reg [31:0] dma_data_out_tlm;
output reg [4:0] checksum_error;
//Internal signals: Packet parsing
reg [10:0] sequence_number;
reg [4:0] sub_assembly_id;
output reg [7:0] parameter_id;
reg [7:0] sync_code;
reg [31:0] transmit_pulse_count;
reg [31:0] transmit_pulse_count_prior;
reg [15:0] length_of_packet;
reg spp_control_count;
//Watchdog timer
//Starts 32 bit counter when first word has been received (i.e. FIFO is not empty)
//Counter will run until checksum has been parsed and transmitted
//If watchdog counter fills up before the DMA CMD Route state machine has completed then watchdog_error_counter will be incremented
reg [31:0] watchdog_timeout;
reg watchdog_timer;
reg [4:0] watchdog_error_counter;
reg purge_cmd; //Flag to dump DMA data until next valid command comes through
reg [31:0] packet_num_count;
reg [31:0] cmd_header_packet;
reg [4:0] parse_state;
reg [31:0] data_packet;
reg wait_counter;
// Checksum registers
reg crcfd;
reg crcnd;
reg crcrdy;
reg [31:0] crcDin;
reg [31:0] crcDout;
reg [15:0] computed_checksum;
wire [15:0] com_checksum;
reg [15:0] transmited_checksum;
assign computed_checksum = com_checksum;
// TLM Checksum registers
output reg tlm_ctu_rdy;
reg tlmfd;
reg tlmnd;
reg tlmrdy;
reg [31:0] tlmDin;
reg [31:0] tlmDout;
reg [15:0] tlm_computed_checksum;
wire [15:0] tlm_com_checksum;
任何建议都会有所帮助。我已经检查过，似乎寄存器数组有问题。 谢谢
所以问题是您不允许使用 reg 数组分配端口。这在 SystemVerilog 和 VHDL 中是允许的，但在 verilog 中是不允许的。