4位数字的除法器

Question

我为分频器编写了一个 vhdl 代码，其中有 16 个组件并带有嵌套循环，但是在合成它时，它在多行中包含特定错误.....

感谢任何帮助。

下面的代码给出了

ERROR:HDLParsers:851 -.vhd" Line 68. Formal cin of CAS with no default value must be associated with an actual value

       library IEEE;
       use IEEE.STD_LOGIC_1164.ALL;
       use IEEE.std_logic_unsigned.all;

       -- Uncomment the following library declaration if using
     -- arithmetic functions with Signed or Unsigned values
      --use IEEE.NUMERIC_STD.ALL;

       -- Uncomment the following library declaration if instantiating
        -- any Xilinx primitives in this code.
       --library UNISIM;
        --use UNISIM.VComponents.all;

          entity blockasli is

       port ( divisor :std_logic_vector(3  downto 0);
       dividend :in std_logic_vector(6  downto 0);
       quotient :out std_logic_vector(3  downto 0);
      remainder :out std_logic_vector(3  downto 0));


    end blockasli;

    architecture behavioral of blockasli is

    -- component declaration ,specifies component interface 

     component CAS port( cin : in  std_logic;
       remainder_in : in  std_logic;
       T : in  std_logic;
       remainder_out : out  std_logic;
       cout : out  std_logic;
       divisor : in  std_logic);    
     end component;

       -- two arrays of four 4 bit vectors - the c and s and r linking       signal between CAS 
      type reg_array is array (3 downto 0) of std_logic_vector(3 downto 0);
       signal c, s: reg_array;
      signal r : std_logic_vector (3 downto 0);

        begin

  GEN_CAS:
 for row in 3 downto 0 generate
 begin
  GEN_CAS0:
  for col in 3 downto 0 generate
   begin
    CAS_X : CAS port map(
      cout => c(row)(col),divisor => divisor(col) , T => not r(row) );

      define_remainder:if row=0 generate 
      begin
      CAS_X : CAS port map(remainder_out=> remainder(col));
      end generate define_remainder;

     linkage_cin_with_c : if col>0 generate 
      begin
      CAS_X : CAS port map( cin=> c(row)(col-1));
      end generate  linkage_cin_with_c ;

      linkage_r_signal_with_cin: if  col=0 generate
         begin
      CAS_X : CAS port map( cin =>  not r(row));
      end generate linkage_r_signal_with_cin;




      dividend_0_to_3 : if col=0 generate
      begin
      CAS_X : CAS port map( remainder_in => dividend(row));
      end generate dividend_0_to_3 ;

       dividend_4_to_6 : if row=3 generate 
        begin
      CAS_X : CAS port map( remainder_in => dividend(col+3));
      end generate dividend_4_to_6 ;



      linkage_s_signal_with_remainder_in : if row<3  generate
      begin
      CAS_X : CAS port map( remainder_in => s(row)(col));
      end generate  linkage_s_signal_with_remainder_in;


      linkage_s_signal_with_remainder_out: if col<3 and row>0  generate
      begin
      CAS_X : CAS port map( remainder_out => s(row-1)(col));
      end generate linkage_s_signal_with_remainder_out;




      linkage_r_signal_with_T: if row>0 and col=3 generate
      begin
      CAS_X : CAS port map( remainder_out => r(row-1));
      end generate linkage_r_signal_with_T;




    end generate GEN_CAS0;

    quotient(row)<= not r(row);

     end generate GEN_CAS;





       end Behavioral;

Answer 1

您需要连接CAS模块的cin口。它在组件声明中定义，但在您的某些端口映射中缺失。

4位数字的除法器

divider of a 4 bit number

components

vhdl

generated-code