Verilog 编码错误

Question

我完全不熟悉 Verilog，对控制台打印的错误有些担心。我知道块总是不允许连线——我不确定 assign 会做什么，但我知道 initialize 肯定不会产生我想要的东西。我不确定如何阅读或解释这些错误，并且我在网上查看过，但似乎没有找到与我的具体错误相关的太多信息。

     module project(input [2:0] p1, input [2:0] p2, input m1, input m2, output reg [6:0] winner);


       // reg mo;  //not allowed 
     // reg mop; //not allowed
always @(*)
begin
if(m1 > 0 )
    case(0)
        0: winner = 16;
        //1: mo = 32; 
        //2: mo = 64;
        //4: mo = 16;
    endcase

if(m2 > 0 )
    case(0)
        0: winner = 1;
        //16: mop = 2;
        //32: mop = 1;
        //64: mop = 4;
    endcase

winner = 0;
case(p1 + p2 + m1 + m2)

        //rock1 & rock2 => tie no one wins
        17: winner = 0; 
        //rock1 & paper2 => player2 won with paper
        33: winner = p2; 
        //rock1 & scissors2 => player1 won with rock
        65: winner = p1; 
        //paper1 & rock2 => player1 won with paper
        18: winner = p1; 
        //paper1 & paper2 => tie no one wins
        34: winner = 0; 
        //paper1 & scissors2 => player2 won with scissors
        66: winner = p2; 
        //scissors1 & rock2 => player2 won with rock 
        20: winner = p2; 
        //scissors1 & paper2 => player1 won with scissors
        36: winner = p1; 
        //scissors1 & scissors2 => tie no one wins
        68: winner = 0;
    endcase
 end
  endmodule

至于我的错误：

WARNING:Par:283 - There are 8 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
WARNING:Par:288 - The signal p1<0>_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal p1<1>_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal p1<2>_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal p2<0>_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal m1_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal m2_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal p2<1>_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal p2<2>_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:PhysDesignRules:367 - The signal <p1<0>_IBUF> is incomplete. The signal
   does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <p1<1>_IBUF> is incomplete. The signal
   does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <p1<2>_IBUF> is incomplete. The signal
   does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <p2<0>_IBUF> is incomplete. The signal
   does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <m1_IBUF> is incomplete. The signal
   does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <m2_IBUF> is incomplete. The signal
   does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <p2<1>_IBUF> is incomplete. The signal
   does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <p2<2>_IBUF> is incomplete. The signal
   does not drive any load pins in the design.

我为多行表示歉意，但我认为发生的情况是一样的，所以如果我能找出一条，我就可以做下一条。如果我的问题令人困惑，我深表歉意，非常感谢您花时间帮助我们查看这些乱七八糟的代码。对于混乱的代码，我深表歉意——如果有人甚至可以将其视为代码的话。谢谢！

Answer 1

警告似乎是由于某些未驱动的输出。您的输出被声明为 reg [6:0] winner，它是 7 位的。它由 p1 或 p2 输入端口驱动，分别声明为 reg [2:0] p1 和 reg [2:0] p2，即每个 3 位。

从不在输出端驱动第 6 位到第 3 位。因此，您的综合工具会发出此警告。

尝试将输出端口声明为 reg [2:0] winner。这可能会解决问题。

有关此警告的更多信息，请参阅 this and the other one 链接。

Answer 2

虽然 sharvil111 所说的是真的 winner 从未被分配任何大于 3 位宽度的东西（请注意，只有在它被注释掉或被分配 winner = 0 否定的时候才正确在你的最后一个案例之前），这不是这些警告的来源。您面临的问题在这一行中：case (p1 + p2 + m1 + m2)。该表达式产生一个 3 位宽的值，因为该表达式中最长的变量是 p1 和 p2 3 位宽。因此，该表达式可以达到的最大值是 3'b7。即使添加到最大位数，它也只会导致最大值 16（3'b111 {=7} + 3'b111 {=7} + 1'b1 {=1} + 1'b1 {=1} = 5'b10000 {=16}；请注意，您需要为 Verilog 做一些事情才能将表达式设为 5 位，并且不是 3，比如添加 5'b0 应该可以）。 case 语句中的值都远高于这两个结果，因此它们都被综合工具删除。除了上面提到的 winner = 0 赋值，无论如何，winner 都将是 7'b0 并且输入的 none 很重要。因此，您会收到警告。

如果您阅读警告，它会显示 loadless signals；这意味着您的设计中有一些信号不驱动任何逻辑，即您的逻辑完全独立于这些信号。因此，综合工具喜欢优化这些信号以节省 space（您不需要执行所有需要的逻辑来获得从未在任何地方使用过的信号！）。它声称有 8 个这样的信号，如果您注意到以下警告，则会继续列出您的所有输入（p1<1>_buf 是 p1[1]，请注意您总共有 8 位的授权，因此 8信号，作为输入）。所有警告都与此问题有关。

查看您的代码，我认为您并不是要添加这些信号。我认为您的意思是将它们连接起来，形成一个 8 位长的向量 ($size(p1) + $size(p2) + $size(m1) + $size(m2))。为此，您需要像这样使用连接运算符 ({})：case ({p1, p2, m1, m2}) 将通过将每个变量的位彼此相邻来生成大小为 8 的向量。示例：p1 = 3'b011; p2 = 3'b101; m1 = 1'b1; m2 = 1'b0; {p1, p2, m1, m2} = 8'b011_101_1_0;

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