ARM Cortex-A7 中的系统控制寄存器
System Control Registers in ARM Cortex-A7
当MCR或MRC指令以不同的cRm或执行时opt2，那么cRn寄存器的状态是什么？
例如，如果 运行:
asm volatile("mcr p15, 0, %0, c9, c13, 0" : : "r"(val))
或
asm volatile("mcr p15, 0, %0, c9, c13, 2" : : "r"(val))
那么，c9和c13哪个寄存器的值会被改变呢？最后一个选项（0 或 2）的作用是什么？here
MCR 和 MRC 指令是通用协处理器指令。这些指令的作用取决于您使用的特定硬件、它具有的协处理器以及操作码和协处理器寄存器操作数的值（opcode1、opcode2、CRn 和 CRm）。协处理器寄存器操作数不一定指实际的协处理器寄存器，因此实际上是附加操作码操作数。
要了解 MCR/MRC 指令的作用，您需要在硬件特定文档中查找它，特定 CPU 这段代码是 运行 下的。因此，对于您的示例，我们需要查看 Cortex-A7's documentation for coprocessor 15，即系统控制 "coprocessor"。此页面列出了可以使用 CRn、opcode1、CRm 中的这些指令访问的系统控制寄存器, opcode2 命令。
在您的两个示例中，CRn 都是 c9，在文档中查找它会导致我们找到 a page describing mostly performance monitoring related registers。在你的第一个例子中 opcode1 是 0，CRm 是 13，而 opcode2 是 0，这个页面告诉我们该指令写入 PMCR 或性能监视器控制寄存器。第二个例子opcode1为0，CRm为13，opcode2为2，表示访问PMNCNTENCLR 或计数启用清除寄存器。
你最好还是认为op1、op2、crn和crm组成了某个寄存器地址。后一条指令将协处理器 15 寄存器 0、c9、c13、2（PMXEVCNTR，性能监视器事件计数寄存器）设置为 C 编译器决定用于变量 'val'.[=12 的寄存器中包含的值=]
对于除性能计数器以外的寄存器：
B3.17.1 按协处理器寄存器编号的 CP15 寄存器汇总
图 B3-26 按 VMSAv7 的主协处理器寄存器编号总结了 CP15 寄存器的分组
实施。
CRn opc1 CRm opc2
c0 {0-2} {c0-c7} {0-7} ¶ ID registers
c1 {0, 4} {c0, c1} {0-7} System control registers
c2 {0, 4} {c0, c1} {0-2} Memory protection and
c3 0 c0 0 control registers
c5 {0, 4} {c0,c1} {0,1} Memory system
c6 {0, 4} c0 {0, 2, 4} fault registers
c7 {0, 4} Various Various ¶ Cache maintenance, address translations, miscellaneous
c8 {0, 4} Various Various TLB maintenance operations
c9 {0-7} Various {0-7} ¶ Reserved for performance monitors and maintenance operations
c10 {0-7} Various {0-7} ¶ Memory mapping registers and TLB operations
c11 {0-7} {c0-c8,c15} {0-7} ¶ Reserved for DMA operations for TCM access
c12 {0, 4} {c0,c1} {0,1} ¶ Security Extensions registers, if implemented
c13 {0, 4} c0 {0-4} ¶ Process, context, and thread ID registers
c14 {0-7} {c0-c15} {0-7} ¶ Generic Timer registers, if implemented
c15 {0-7} {c0-c15} {0-7} ¶ IMPLEMENTATION DEFINED registers
Read-only Read/Write Write-only ¶ Access depends on the implementation
Figure B3-26 CP15 register grouping by primary coprocessor register, CRn, VMSA implementation
关于调试寄存器，有说明：
C6.4.1 使用 CP14 访问调试寄存器
访问 CP14 接口中可见的寄存器通常使用以下协处理器指令：
• MRC 用于读访问。
• 用于写访问的 MCR。
In addition, the following coprocessors instructions are defined for specific registers accesses:
MRRC Read access to the Debug ROM Address Register, DBGDRAR, and the Debug Self Address Offset
Register, DBGDSAR, in an implementation that includes the Large Physical Address Extension.
STC Read access to the Host to Target Data Transfer Register, DBGDTRRXint.
LDC Write access to the Target to Host Data Transfer Register, DBGDTRTXint.
Form of MRC and MCR instructions
The form of the MRC and MCR instructions used for accessing debug registers through the CP14 interface is:
MRC p14, 0, <Rt>, <CRn>, <CRm>, <opc2> ; Read
MCR p14, 0, <Rt>, <CRn>, <CRm>, <opc2> ; Write
Where <Rt> refers to any of the ARM core registers R0-R14. Use of R13 is UNPREDICTABLE in Thumb and
ThumbEE states, and is deprecated in ARM state. <CRn>, <CRm>, and <opc2> are mapped from the debug register
number as shown in Figure C6-1
The use of the MRC APSR_nzcv form of the MRC instruction is permitted for reads of the DBGDSCRint only. Use with
other registers is UNPREDICTABLE. See CP14 interface 32-bit access instructions, required in all versions of the
Debug architecture on page C6-2124 for more information.
For accesses to the debug registers, <CRn> <= 0b0111 and therefore bit[10] of the value in the figure is 0.
10 9 8 7 6 5 4 3 2 1 0
Value 0 Register number[9:0]
Arguments CRn[3:0] opc2[2:0] CRm[3:0]
Figure C6-1 Mapping from debug register number to CP14 instruction arguments
当MCR或MRC指令以不同的cRm或执行时opt2，那么cRn寄存器的状态是什么？ 例如，如果 运行:
asm volatile("mcr p15, 0, %0, c9, c13, 0" : : "r"(val))
或
asm volatile("mcr p15, 0, %0, c9, c13, 2" : : "r"(val))
那么，c9和c13哪个寄存器的值会被改变呢？最后一个选项（0 或 2）的作用是什么？here
MCR 和 MRC 指令是通用协处理器指令。这些指令的作用取决于您使用的特定硬件、它具有的协处理器以及操作码和协处理器寄存器操作数的值（opcode1、opcode2、CRn 和 CRm）。协处理器寄存器操作数不一定指实际的协处理器寄存器，因此实际上是附加操作码操作数。
要了解 MCR/MRC 指令的作用，您需要在硬件特定文档中查找它，特定 CPU 这段代码是 运行 下的。因此，对于您的示例，我们需要查看 Cortex-A7's documentation for coprocessor 15，即系统控制 "coprocessor"。此页面列出了可以使用 CRn、opcode1、CRm 中的这些指令访问的系统控制寄存器, opcode2 命令。
在您的两个示例中，CRn 都是 c9，在文档中查找它会导致我们找到 a page describing mostly performance monitoring related registers。在你的第一个例子中 opcode1 是 0，CRm 是 13，而 opcode2 是 0，这个页面告诉我们该指令写入 PMCR 或性能监视器控制寄存器。第二个例子opcode1为0，CRm为13，opcode2为2，表示访问PMNCNTENCLR 或计数启用清除寄存器。
你最好还是认为op1、op2、crn和crm组成了某个寄存器地址。后一条指令将协处理器 15 寄存器 0、c9、c13、2（PMXEVCNTR，性能监视器事件计数寄存器）设置为 C 编译器决定用于变量 'val'.[=12 的寄存器中包含的值=]
对于除性能计数器以外的寄存器： B3.17.1 按协处理器寄存器编号的 CP15 寄存器汇总 图 B3-26 按 VMSAv7 的主协处理器寄存器编号总结了 CP15 寄存器的分组 实施。
CRn opc1 CRm opc2
c0 {0-2} {c0-c7} {0-7} ¶ ID registers
c1 {0, 4} {c0, c1} {0-7} System control registers
c2 {0, 4} {c0, c1} {0-2} Memory protection and
c3 0 c0 0 control registers
c5 {0, 4} {c0,c1} {0,1} Memory system
c6 {0, 4} c0 {0, 2, 4} fault registers
c7 {0, 4} Various Various ¶ Cache maintenance, address translations, miscellaneous
c8 {0, 4} Various Various TLB maintenance operations
c9 {0-7} Various {0-7} ¶ Reserved for performance monitors and maintenance operations
c10 {0-7} Various {0-7} ¶ Memory mapping registers and TLB operations
c11 {0-7} {c0-c8,c15} {0-7} ¶ Reserved for DMA operations for TCM access
c12 {0, 4} {c0,c1} {0,1} ¶ Security Extensions registers, if implemented
c13 {0, 4} c0 {0-4} ¶ Process, context, and thread ID registers
c14 {0-7} {c0-c15} {0-7} ¶ Generic Timer registers, if implemented
c15 {0-7} {c0-c15} {0-7} ¶ IMPLEMENTATION DEFINED registers
Read-only Read/Write Write-only ¶ Access depends on the implementation
Figure B3-26 CP15 register grouping by primary coprocessor register, CRn, VMSA implementation
关于调试寄存器，有说明： C6.4.1 使用 CP14 访问调试寄存器 访问 CP14 接口中可见的寄存器通常使用以下协处理器指令： • MRC 用于读访问。 • 用于写访问的 MCR。
In addition, the following coprocessors instructions are defined for specific registers accesses:
MRRC Read access to the Debug ROM Address Register, DBGDRAR, and the Debug Self Address Offset
Register, DBGDSAR, in an implementation that includes the Large Physical Address Extension.
STC Read access to the Host to Target Data Transfer Register, DBGDTRRXint.
LDC Write access to the Target to Host Data Transfer Register, DBGDTRTXint.
Form of MRC and MCR instructions
The form of the MRC and MCR instructions used for accessing debug registers through the CP14 interface is:
MRC p14, 0, <Rt>, <CRn>, <CRm>, <opc2> ; Read
MCR p14, 0, <Rt>, <CRn>, <CRm>, <opc2> ; Write
Where <Rt> refers to any of the ARM core registers R0-R14. Use of R13 is UNPREDICTABLE in Thumb and
ThumbEE states, and is deprecated in ARM state. <CRn>, <CRm>, and <opc2> are mapped from the debug register
number as shown in Figure C6-1
The use of the MRC APSR_nzcv form of the MRC instruction is permitted for reads of the DBGDSCRint only. Use with
other registers is UNPREDICTABLE. See CP14 interface 32-bit access instructions, required in all versions of the
Debug architecture on page C6-2124 for more information.
For accesses to the debug registers, <CRn> <= 0b0111 and therefore bit[10] of the value in the figure is 0.
10 9 8 7 6 5 4 3 2 1 0
Value 0 Register number[9:0]
Arguments CRn[3:0] opc2[2:0] CRm[3:0]
Figure C6-1 Mapping from debug register number to CP14 instruction arguments