在 VHDL 中实现 50ns 延迟

Question

我正在向 A/D 转换器发送数据，我需要将命令数据从 clk_19khz 延迟至少 50ns。这是我到目前为止所拥有的。如何在 clk_19khz 和我的 A/D 的第一个 Dout 位之间插入 50ns 的延迟，这是 A/D 的要求？我正在使用 Xilinx FPGA。感谢您的帮助！

         library IEEE;
        use IEEE.STD_LOGIC_1164.ALL;

         -- Uncomment the following library declaration if using
         -- arithmetic functions with Signed or Unsigned values
         --use IEEE.NUMERIC_STD.ALL;

         -- Uncomment the following library declaration if instantiating
         -- any Xilinx primitives in this code.
         --library UNISIM;
         --use UNISIM.VComponents.all;

      entity PSOL is
        Port ( clk : in  STD_LOGIC;
               clk_19khz : OUT std_logic;
               Dout :out std_logic);
        end PSOL;

     architecture Behavioral of PSOL is
         signal temp : std_logic;
         signal count : integer range 0 to 1301 := 0; --1301
         signal temp2 : std_logic;
         signal dcount : integer range 0 to 11 := 0; --
         signal start : std_logic  := '1'; -- indicates the start of                      
         signal parity : std_logic := '1'; --used to varify data sent
         signal stop : std_logic := '0'; --indicate when word/command has                             
       --signal chip_select : bit :='1'; -- active low



     begin
       process (clk)
         begin
            if (clk' EVENT AND clk='1') then
                if (count = 1301) then --1301
                    temp <= not(temp);
                    count <=0;
                else
                    count <= count + 1;     
                end if;
            end if;
     end process;

        clk_19khz <= temp;
         temp2 <= temp;


      process (temp2)
        begin
            If (temp2' EVENT and temp2 ='0') then

                dcount <= dcount + 1;
                parity <= '1';
                stop <= '0';
                start <='1';
            if (dcount < 12 and start = '1' and stop = '0') then
                CASE dcount is
                  when 1 => Dout <= start; -- need delay 50ns before this 
                  when 2 => Dout <= '0';
                  when 3 => Dout <= '1';
                  when 4 => Dout <= '0';
                  when 5 => Dout <= '1';
                  when 6 => Dout <= '0';
                  when 7 => Dout <= '0';
                  when 8 => Dout <= '1';
                  when 9 => Dout <= '1';
                  when 10 => Dout <= parity;
                  when 11 => Dout <= '0';
                  when others => null;
                 end case;
            end if;
        end if;             
        --dcount <= 0;
        --start <='1';

    end process;



 end Behavioral;

Answer 1

您的时钟 (50 MHz) 的周期为 20 ns。因此，您需要一个模 3 计数器来计算至少 3 个时钟脉冲的延迟，从而延迟 60 ns.

声明：

signal delay_en : std_logic;
signal delay_us : unsigned(1 downto 0) := (others => '0');
signal delay_ov : std_logic;

用法：

process(clk)
begin
  if rising_edge(clk) then
    if (delay_en = '1') then
      delay_us <= delay_us + 1;
    else
      delay_us <= (others => '0');
    end if;
  end if;
end process;
delay_ov <= '1' when (delay_us = 2) else '0';

您当前的实施需要在等待时间跨度时驱动 delay_en。如果延迟结束，它会发出信号 delay_ov（ov = 溢出）。您的解决方案可以使用它来继续 in 算法。您的代码还应该解除断言 delay_en，什么将计数器清除为 0。

在 VHDL 中实现 50ns 延迟

implementing a 50ns delay in VHDL

vhdl

xilinx

spi

xilinx-ise