VHDL FILE_OPEN 没有 return 正确的状态

Question

我在 VHDL 中有一个程序，它从文件中读取一行，并且应该根据该行的各个字符分配信号值。我面临的问题是我的 FILE_OPEN 语句似乎不起作用。

FILE_OPEN(fstatus, mem_file, "H:\memfile.dat", READ_MODE);

fstatus 总是 OPEN_OK 如果未初始化或它初始化的值永远不会改变。程序的完整代码如下。

library IEEE; 
use IEEE.STD_LOGIC_1164.all; use STD.TEXTIO.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use IEEE.NUMERIC_STD.all;
--use ieee.std_logic_1164_additions.all
entity imem is -- instruction memory
 port(a:  in  STD_LOGIC_VECTOR(5 downto 0);
      rd: out STD_LOGIC_VECTOR(31 downto 0));
 end;
architecture behave of imem is
begin
 process is
   file mem_file: TEXT;
   variable L, my_line: line;
   variable L_ch : string(1 to 8);
   variable ch, charac: character;
   variable i, index, result: integer;
   variable valid : boolean; -- to record whether a read is successful or not
   variable fstatus: FILE_OPEN_STATUS;
   type ramtype is array (63 downto 0) of STD_LOGIC_VECTOR(31 downto 0);
   variable mem: ramtype;
begin
  -- initialize memory from file
for i in 0 to 63 loop -- set all contents low
  mem(i) := (others => '0'); 
end loop;
index := 0; 
 --fstatus := NAME_ERROR;
FILE_OPEN(fstatus, mem_file, "H:\memfile.dat", READ_MODE);
 report "Got status from file: '" & FILE_OPEN_STATUS'image(fstatus) & "'";

 IF fstatus = OPEN_OK THEN

while not endfile(mem_file) loop


  readline(mem_file, L);
    report "Got line from file: '" & L.all & "'";
    result := 0;    
  for i in 1 to 8 loop
    read(L, ch, valid);
      --write(my_line, string'(L_ch));    -- formatting
      --writeline(output, my_line);

      if (L'length = 0) then report "line empty " & integer'image(index)
            severity error;
      end if;


      --ch := L_ch(i);
      read(L, charac);

    if '0' <= ch and ch <= '9' then 
        result := character'pos(ch) - character'pos('0');
    elsif 'a' <= ch and ch <= 'f' then
       result := character'pos(ch) - character'pos('a')+10;
    else report "Format error on line " & integer'image(index) & character'image(ch) & character'image(charac) & boolean'image(valid) --& to_string(L_ch)
         severity error;
    end if;
    mem(index)(35-i*4 downto 32-i*4) :=std_logic_vector(to_unsigned(result,4));
  end loop;
  index := index + 1;
end loop;



-- read memory
loop
  rd <= mem(to_integer(unsigned(a)));
  wait on a;
end loop;
 file_close(mem_file);
 end if;
 wait;
 end process;
end;

我正在使用 Quartus Prime Lite 进行综合。

Answer 1

Altera 的 Quartus 不支持综合中的 VHDL 文件 I/O 功能。据我所知，Quartus 确实支持 Verilog 文件 I/O 综合功能。

查看 altsyncram（搜索 $readmemh(...)）实现以获取有关 Verilog 文件 I/O 的更多详细信息，用于在综合初始化 RAM 时读取 *.mif 文件。

VHDL FILE_OPEN 没有 return 正确的状态

VHDL FILE_OPEN does not return correct status

io

file

vhdl

intel-fpga

quartus