当输出应为 1 时，它变为未知

Question

所以对于一项学校作业，我们必须使用不同的模块制作一个时钟，我有一个上下计数器和一个有限状态机。我应该能够按下一个按钮，这样计数器就会增加一或减少一，这会持续数小时、数分钟和数秒。问题出在我的 fsm 的测试台上。当你添加一个数字时，up_down 信号应该变为 1，这样计数器就知道它必须向上计数，但是当这种情况发生时，信号变为未知，而当我想减少它时，信号又回到 0，因为它应该.

我一直在寻找为什么它可以做到这一点，但没有任何线索，有人知道为什么吗？我将发布我的代码和测试平台的屏幕截图。

a) 有限状态机

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity tijd_FSM is
    Port ( clk_1ms  : in    std_logic;
              BTU       : in  std_logic;
           BTD      : in  STD_LOGIC;
              BTR           : in    std_logic;
              mo_tijd   : in    std_logic;
              EupH      : out std_logic;
              EdownH        : out std_logic;
              EupM      : out std_logic;
              EdownM        : out std_logic;
              EupS      : out std_logic;
              EdownS        : out std_logic;
              up_down   : out std_logic;
              blink_tijd: out std_logic_vector (1 downto 0)
              );        
end tijd_FSM;

architecture Behavioral of tijd_FSM is
type state is (s0, s1, s2, s3);
signal present_state, next_state : state;
begin

state_reg: process (clk_1ms)
begin
    if rising_edge(clk_1ms) then
        if(BTR = '1' and mo_tijd = '1') then
            present_state <= next_state;
        else
            present_state <= present_state;
        end if;
    end if;
end process;

--state machine process.
outputs: process (present_state, BTU, BTD)
begin
  case present_state is 
    when s0 =>      --Gewone weergave
     blink_tijd <= "00";
     up_down <= '0';

    when s1 =>       --Instellen UU 
            if(BTU ='1') then 
                up_down <= '1';
                EupH <= '1';
            elsif(BTD='1') then
                up_down <= '0';
                EdownH <= '1';
            else
                EupH <= '0';
                EdownH <= '0'; 
        end if;
        blink_tijd <= "10";


     when s2 =>         --Instellen MM
        if(BTU ='1') then
            up_down <= '1';
            EupM <= '1';
        elsif(BTD='1') then
            up_down <= '0';
            EdownM <= '1';
        else
            EupM <= '0';
            EdownM <= '0';
        end if;
        blink_tijd <= "10";


     when s3 =>         --Instellen SS
        if(BTU ='1') then
            up_down <= '1';
            EupS <= '1';
        elsif(BTD='1') then
            up_down <= '0';
            EdownS <= '1';
        else
            EupS <= '0';
            EdownS <= '0';
        end if;
        blink_tijd <= "01";

        when others => null;

  end case;
end process;


nxt_state: process (BTR, present_state)
begin   
    case present_state is
        when s0 =>
        if BTR = '1' then next_state <= s1;
        else next_state <= s0;
        end if;

        when s1 =>
        if BTR = '1' then next_state <= s2;
        else next_state <= s1;
        end if;

        when s2 =>
        if BTR = '1' then next_state <= s3;
        else next_state <= s2;
        end if;

        when s3 =>
        if BTR = '1' then next_state <= s0;
        else next_state <= s3;
        end if;

        when others => next_state <= s0;

    end case;
end process;
end Behavioral;

b) 测试平台

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;

ENTITY tb_tijd_FSM IS
END tb_tijd_FSM;

ARCHITECTURE behavior OF tb_tijd_FSM IS 

    -- Component Declaration for the Unit Under Test (UUT)

    COMPONENT tijd_FSM
    PORT(
         clk_1ms : IN  std_logic;
         BTU : IN  std_logic;
         BTD : IN  std_logic;
         BTR : IN  std_logic;
         mo_tijd : IN  std_logic;
         EupH : OUT  std_logic;
         EdownH : OUT  std_logic;
         EupM : OUT  std_logic;
         EdownM : OUT  std_logic;
         EupS : OUT  std_logic;
         EdownS : OUT  std_logic;
         up_down : OUT  std_logic;
         blink_tijd : OUT  std_logic_vector(1 downto 0)
        );
    END COMPONENT;


   --Inputs
   signal clk_1ms : std_logic := '0';
   signal BTU : std_logic := '0';
   signal BTD : std_logic := '0';
   signal BTR : std_logic := '0';
   signal mo_tijd : std_logic := '0';

    --Outputs
   signal EupH : std_logic;
   signal EdownH : std_logic;
   signal EupM : std_logic;
   signal EdownM : std_logic;
   signal EupS : std_logic;
   signal EdownS : std_logic;
   signal up_down : std_logic;
   signal blink_tijd : std_logic_vector(1 downto 0);

   -- Clock period definitions
   constant clk_1ms_period : time := 1 ms;

BEGIN

    -- Instantiate the Unit Under Test (UUT)
   uut: tijd_FSM PORT MAP (
          clk_1ms => clk_1ms,
          BTU => BTU,
          BTD => BTD,
          BTR => BTR,
          mo_tijd => mo_tijd,
          EupH => EupH,
          EdownH => EdownH,
          EupM => EupM,
          EdownM => EdownM,
          EupS => EupS,
          EdownS => EdownS,
          up_down => up_down,
          blink_tijd => blink_tijd
        );

   -- Clock process definitions
   clk_1ms_process :process
   begin
        clk_1ms <= '0';
        wait for clk_1ms_period/2;
        clk_1ms <= '1';
        wait for clk_1ms_period/2;
   end process;


   -- Stimulus process
   stim_proc: process
   begin        
        up_down <= '0';
        mo_tijd <= '1';

        --Hij begint in state s0

        wait for 1 ms;

        BTR <= '1'; --s1
        wait for 1 ms;
        BTR <= '0'; 
        wait for 1 ms;
        BTU <= '1';
        wait for 1 ms;
        BTU <= '0';
        wait for 1 ms;
        BTD <= '1';
        wait for 1 ms;
        BTD <= '0';
        wait for 1 ms;

        BTR <= '1'; --s2
        wait for 1 ms;
        BTR <= '0';
        wait for 1 ms;
        BTU <= '1';
        wait for 1 ms;
        BTU <= '0';
        wait for 1 ms;
        BTD <= '1';
        wait for 1 ms;
        BTD <= '0';
        wait for 1 ms;

        BTR <= '1'; -- s3
        wait for 1 ms;
        BTR <= '0';
        wait for 1 ms;
        BTU <= '1';
        wait for 1 ms;
        BTU <= '0';
        wait for 1 ms;
        BTD <= '1';
        wait for 1 ms;
        BTD <= '0'; 
      wait;
   end process;

END;

c) 波形图

Answer 1

在 stim_proc 中你有 up_down <= '0'，它驱动 0 在与你的状态机输出连接的相同信号上。

只要状态机还驱动 0，一切都很好，因为组合解析为 0。但是，当状态机驱动 1 时，分辨率为 X，未定义。

据我所知，stim_proc 没有理由驱动这个信号，所以删除那条线应该会给你想要的。

当输出应为 1 时，它变为未知

When an output should go to 1, it goes to unknown

vhdl