初始化 systemverilog (ovm) 参数化 class 数组

Question

我想监控多个分析端口，"publish" 项目通过一个分析端口。它适用于预定义的项目类型，但无法参数化。

代码：

   class ovm_analysis_sink #(int NUM_PORTS = 1, type T = ovm_object ) extends ovm_component;

 // .......................................
 `ovm_component_param_utils(ovm_analysis_sink#(NUM_PORTS,T))
 // .......................................

 ovm_analysis_imp #(T,ovm_analysis_sink) mon_analysis_imp[NUM_PORTS-1:0];
 ovm_analysis_port #(T) mon_analysis_port = new("mon_analysis_port", this);

 virtual function void build() ;
 string inst;
for(int i=0 ;i < NUM_PORTS ;i++ )
  begin 
    $sformat(inst,"mon_analysis_imp_%0d",i);
mon_analysis_imp[i] = new(inst,this);
  end

super.build() ;

endfunction : build

analysis_sink的用法：

 ovm_analysis_sink #(3,a_type) a_item_sink;

错误信息：

Error-[ICTTFC] Incompatible complex type usage ovm_tb.sv, 42
Incompatible complex type usage in task or function call.
The following expression is incompatible with the formal parameter of the function. 
The type of the actual is 'class $unit::ovm_analysis_sink#(3,class $unit::a_type)', 
while the type of the formal is 'class $unit::ovm_analysis_sink#(1,class ovm_pkg::ovm_object)'. 
Expression: this  Source info: ovm_analysis_imp::new(inst, this)

Answer 1

错误显示类型不兼容。这意味着实现端口的实际（运行-time）和正式（编译时）arguments/types 是不一样的。

声明分析端口时出错。如上所示声明端口会创建 handle 类型 uvm_analysis_sink #(1,uvm_object) 的分析导入端口，而您希望它的类型为 uvm_analysis_sink #(3,a_type).

所以，声明如下：

ovm_analysis_imp #(T,ovm_analysis_sink#(NUM_PORTS,T)) mon_analysis_imp[NUM_PORTS-1:0];

这将消除类型冲突并使其类型分配兼容。现在任何 参数覆盖 都可以工作。

我在 EDAPlayground for reference. Similar applies to your OVM testbench. For further information refer to this 论坛问题上创建了一个示例 UVM 代码。

初始化 systemverilog (ovm) 参数化 class 数组

initialize systemverilog (ovm) parameterized class array

system-verilog

uvm