Verilog 阻塞赋值不阻塞

Question

我对Verilog阻塞赋值有问题，在仿真中它似乎没有阻塞。特别是在第二个 always@ 块中。我需要第一个去“1"only forv1 unit (clock cycle?), but it simultaneosly goes "1”和“0”。当我用 rst = #10 1'b0; 替换两个 rst = 1'b0; 然后在模拟中我可以看到第一个在 10 个时间单位内变为“1”。有人可以帮助我吗？

module testled(
input clk,
output reg out
);
 reg [23:0] counter;
 reg rst;


 initial begin
    out = 1'b0;
    rst = 1'b0;
    counter = 24'b000000000000000000000000;
end
always @(posedge clk, posedge rst) begin
    if(rst) begin
        counter = 24'b000000000000000000000000;
    end
    else begin
        counter = counter + 1;
    end
end

always @(posedge clk) begin
    case (out)
        1'b1 : begin
            if (counter[5]) begin
                rst = 1'b1;
                out = 1'b0;
                rst =1'b0;
            end
            else begin
                out = out;
            end             
        end
        1'b0 : begin
            if (counter[3]) begin
                rst = 1'b1;
                out = 1'b1;
                rst = 1'b0;
            end
            else begin
                out = out;
            end             
        end         
    endcase
end

结束模块

Answer 1

出于模拟目的，您可以这样做：

initial begin
  out = 1'b1;
  #10ns out = 1'b0;
  #20ns out = 1'b1;
  #30ns out = 1'b0;
end

但这不可综合，因此对您的最终申请没有帮助。

对于顺序（时钟）逻辑，高电平或低电平的时间必须是整数个时钟周期。使用 Counter 作为状态并将其组合解码为输出。

always @(posedge clk,  rst) begin
  if(rst) begin
    counter <= 'b0;
  end
  else begin
    counter <= counter + 1;
  end
end

always @* begin
  if (counter < 10) begin
    out = 1'b0;
  end 
  else if (counter < 30) begin
    out = 1'b1;
  end
  else if (counter < 50) begin
    out = 1'b0;
  end
  else if (counter < 90) begin
    out = 1'b1;
  end
  else begin
    out = 1'b0;
  end
end

Verilog 阻塞赋值不阻塞

Verilog blocking assignment not blocking

verilog

hdl

system-verilog