VHDL 为什么状态 S0 在不应该处于活动状态时处于活动状态？

Question

我在处理这段代码时遇到了一些问题。似乎状态 S0 始终处于活动状态，即使它不应该处于活动状态。看起来这个状态的输出是反转的（当它应该被禁用时激活）。有任何想法吗？模拟打印在底部。谢谢

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity ControlUnit is
     port(clk           : in  std_logic;
          reset         : in  std_logic;
          validTime     : in  std_logic;
          timeData      : in  std_logic_vector(3 downto 0);
          writeEnable   : out std_logic;
          writeAddress  : out std_logic_vector(3 downto 0);
          averageReady  : out std_logic);
end ControlUnit;

architecture Behavioral of ControlUnit is
    type TState is (S0, S1, S2, S3, S4, S5);
    signal PState, NState: TState;
begin

    sync_proc: process(clk, reset)
    begin
        if(reset = '1') then
            PState <= S0;
        elsif(rising_edge(clk)) then
            PState <= NState;
        end if;
    end process;

    comb_proc: process(PState, validTime, timeData)
    begin
        averageReady <= '0';
        writeEnable <= '0';
        case PState is
            when S0 =>
                if(validTime = '1') then
                    writeEnable <= '1';
                    NState <= S1;
                else
                    NState <= S0;
                end if;
            when S1 =>
                if(validTime = '1') then
                    writeEnable <= '1';
                    NState <= S2;
                else
                    NState <= S1;
                end if;
            when S2 =>
                if(validTime = '1') then
                    writeEnable <= '1';
                    NState <= S3;
                else
                    NState <= S2;
                end if;
            when S3 =>
                if(validTime = '1') then
                    writeEnable <= '1';
                    NState <= S4;
                else
                    NState <= S3;
                end if;
            when S4 =>
                if(validTime = '1') then
                    writeEnable <= '1';
                    NState <= S5;
                else
                    NState <= S4;
                end if;
            when S5 =>
                averageReady <= '1';
                NState <= S0;
            when others =>
                NState <= S0;
        end case;
    end process;

    with PState select
        writeAddress <= "0000" when S0,
                             "0001" When S1,
                             "0010" when S2,
                             "0011" when S3,
                             "0100" when S4,
                             "XXXX" when others;
end Behavioral;

这是模拟的打印：

（可点击）

Answer 1

您的代码一切正常。为什么您认为 S0 状态始终处于活动状态？你不能从波形上说出来，因为你不知道编码方案。另一方面，您 writeAddress 信号不断变化意味着您的状态机改变了它的状态。

VHDL 为什么状态 S0 在不应该处于活动状态时处于活动状态？

VHDL Why is state S0 active when it isn't supposed to be?

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