SystemVerilog: Assignment pattern element <name>: Element widths don't match (error: vlog-7034)

Question

我正在尝试（未成功）使用多维数组发送硬编码常量数组，这些数组可以由其他模块中的计数器索引。

我目前的策略是使用参数数组，编译和部署，但在硬件上只考虑每个数组元素中的第一位一次。这反映在 RTL 视图中，所以我转到 modelsim 并收到此错误：

Error: (vlog-7034) <path>(<line>): Array assignment to type 'reg[9:0] $[19:0]' from type 'reg $[19:0]':  Assignment pattern element 'NoMove':  Element widths (10, 1) don't match

我的代码在这里：

module EScheduler(input Clk, Reset,
                output reg [9:0] ESchedCtr,
                output reg [9:0] ESchedX [NE - 1:0][NM - 1:0], ESchedY [NE - 1:0][NM - 1:0],
                output reg [9:0] EShipInitialX [NE - 1:0], EShipInitialY [NE - 1:0],
                output reg ESchedFire [NE - 1:0][NM - 1:0]);
    logic clkby2;
    initial clkby2 = 0;
    always_ff @ (posedge Clk)
    begin
        clkby2 <= ~clkby2;
    end
    parameter PlusOne = 10'b1;
    parameter MinusOne = (~(PlusOne) + 10'b1);
    parameter reg NoMove [NM - 1:0] = '{10'd0, 10'd0, 10'd0, 10'd0, 10'd0,
                                        10'd0, 10'd0, 10'd0, 10'd0, 10'd0,
                                        10'd0, 10'd0, 10'd0, 10'd0, 10'd0,
                                        10'd0, 10'd0, 10'd0, 10'd0, 10'd0};
    parameter reg CircleX [NM - 1:0] = '{   PlusOne, PlusOne, PlusOne, PlusOne, PlusOne,
                                            MinusOne, MinusOne, MinusOne, MinusOne, MinusOne,
                                            MinusOne, MinusOne, MinusOne, MinusOne, MinusOne,
                                            PlusOne, PlusOne, PlusOne, PlusOne, PlusOne};
    parameter reg CircleY [NM - 1:0] = '{   PlusOne, PlusOne, PlusOne, PlusOne, PlusOne,
                                            PlusOne, PlusOne, PlusOne, PlusOne, PlusOne,
                                            MinusOne, MinusOne, MinusOne, MinusOne, MinusOne,
                                            MinusOne, MinusOne, MinusOne, MinusOne, MinusOne};
    parameter reg BackAndForth [NM - 1:0] = '{  PlusOne, MinusOne, PlusOne, MinusOne, PlusOne,
                                                MinusOne, PlusOne, MinusOne, PlusOne, MinusOne,
                                                PlusOne, MinusOne, PlusOne, MinusOne, PlusOne,
                                                MinusOne, PlusOne, MinusOne, PlusOne, MinusOne};
    parameter reg FireOnFrame13 [NM - 1:0] = '{1'b0, 1'b0, 1'b0, 1'b0, 1'b0,
                                    1'b0, 1'b0, 1'b0, 1'b0, 1'b0,
                                    1'b0, 1'b0, 1'b1, 1'b1, 1'b1,
                                    1'b0, 1'b0, 1'b0, 1'b0, 1'b0 };
    always_ff @ (posedge clkby2)
    begin
        if(Reset == 1'b1)
        begin
            ESchedCtr <= 10'b0;
        end
        else
        begin
            if(ESchedCtr >= NM - 1)
                ESchedCtr <= 10'b0;
            else
                ESchedCtr <= ESchedCtr + 10'b1;
        end
        ESchedFire <= '{ FireOnFrame13, FireOnFrame13,
                FireOnFrame13, FireOnFrame13,
                FireOnFrame13, FireOnFrame13,
                FireOnFrame13, FireOnFrame13,
                FireOnFrame13, FireOnFrame13 };
    end
    always_comb
    begin
        EShipInitialX = '{10'd020, 10'd080, 10'd140, 10'd200, 10'd260, 10'd320, 10'd380, 10'd440, 10'd500, 10'd560};
        EShipInitialY = '{10'd040, 10'd040, 10'd040, 10'd040, 10'd040, 10'd040, 10'd040, 10'd040, 10'd040, 10'd040};
        ESchedX = '{9: CircleX, 8: BackAndForth, 7: CircleY, 6: NoMove, 5: NoMove,
                    4: NoMove, 3: NoMove, 2: NoMove, 1: NoMove, 0: NoMove};
        ESchedY = '{CircleY, NoMove, CircleX, NoMove, NoMove,
                    NoMove, NoMove, NoMove, NoMove, NoMove};
    end
endmodule

我开始使用此处提供的答案：https://verificationacademy.com/forums/systemverilog/working-multi-dimensional-associative-arrays

也就是用冒号来定义每个元素所在的索引，但是一直没有成功。 Google 搜索中没有提及此错误。

Answer 1

愚蠢的错误，幸运的是。我忘记在参数声明中包含字段宽度：

parameter reg [9:0] CircleX [NM - 1:0] = '{   PlusOne, PlusOne, PlusOne, PlusOne, PlusOne,
                                        MinusOne, MinusOne, MinusOne, MinusOne, MinusOne,
                                        MinusOne, MinusOne, MinusOne, MinusOne, MinusOne,
                                        PlusOne, PlusOne, PlusOne, PlusOne, PlusOne};
parameter reg [9:0] CircleY [NM - 1:0] = '{   PlusOne, PlusOne, PlusOne, PlusOne, PlusOne,
                                        PlusOne, PlusOne, PlusOne, PlusOne, PlusOne,
                                        MinusOne, MinusOne, MinusOne, MinusOne, MinusOne,
                                        MinusOne, MinusOne, MinusOne, MinusOne, MinusOne};
parameter reg [9:0] BackAndForth [NM - 1:0] = '{  PlusOne, MinusOne, PlusOne, MinusOne, PlusOne,
                                            MinusOne, PlusOne, MinusOne, PlusOne, MinusOne,
                                            PlusOne, MinusOne, PlusOne, MinusOne, PlusOne,
                                            MinusOne, PlusOne, MinusOne, PlusOne, MinusOne};
parameter reg FireOnFrame13 [NM - 1:0] = '{1'b0, 1'b0, 1'b0, 1'b0, 1'b0,
                                1'b0, 1'b0, 1'b0, 1'b0, 1'b0,
                                1'b0, 1'b0, 1'b1, 1'b1, 1'b1,
                                1'b0, 1'b0, 1'b0, 1'b0, 1'b0 };

我将保留此解决方案，以便其他人可以从搜索结果中看到此错误代码中获益。

SystemVerilog: Assignment pattern element <name>: Element widths don't match (error: vlog-7034)

SystemVerilog: Assignment pattern element <name>: Element widths don't match (error: vlog-7034)

arrays

fpga

hdl

system-verilog