Chisel 语言如何最好地使用队列?
Chisel language how to best use Queues?
我是新手,如果有人能解释一下作用:
1- 队列
2-解耦IO
3-解耦
3-有效IO
4- 有效
这段凿码正确吗?
...
val a = Decoupled()
val b = Decoupled()
val c = Decoupled()
...
val Reg_a = Reg(UInt())
val Reg_b = Reg(UInt())
...
when(io.a.valid && io.a.ready && io.b.valid && io.b.ready && io.c.valid && io.c.ready)
{
Reg_a := io.a.bits.data
Reg_b := io.b.bits.data
}
io.c.bits := Reg_a & Reg_b
...
Module.io.a <> Queue(Module_1.io.a_1)
Module.io.b <> Queue(Module_1.io.b_1)
Module_1.io.c_1 <> Queue(Module.io.c)
问候!
- Queue是一个硬件模块,它实现了一个先进先出的队列,带有DecoupledIO输入和输出
- DecoupledIO 是一个 ready/valid 接口类型,成员就绪、有效和位
- Decoupled 是从其他类型构造 DecoupledIO 的助手
- ValidIO 类似于DecoupledIO,只是它只有valid和bits
- Valid类似于Decoupled构造ValidIOs
我不知道代码试图做什么,但这是一个具有 2 个 DecoupledIO 输入和 1 个 DecoupledIO 输出的模块示例。它用队列缓冲输入,然后将输出连接到输入的总和:
import chisel3._
import chisel3.util._
class QueueModule extends Module {
val io = IO(new Bundle {
val a = Flipped(Decoupled(UInt(32.W))) // valid and bits are inputs
val b = Flipped(Decoupled(UInt(32.W)))
val z = Decoupled(UInt(32.W)) // valid and bits are outputs
})
// Note that a, b, and z are all of type DecoupledIO
// Buffer the inputs with queues
val qa = Queue(io.a) // io.a is the input to the FIFO
// qa is DecoupledIO output from FIFO
val qb = Queue(io.b)
// We only dequeue when io.z is ready
qa.nodeq() // equivalent to qa.ready := false.B
qb.nodeq()
// When qa and qb have valid inputs and io.z is ready for an output
when (qa.valid && qb.valid && io.z.ready) {
io.z.enq(qa.deq() + qb.deq())
/* The above is short for
io.z.valid := true.B
io.z.bits := qa.bits + qb.bits
qa.ready := true.B
qb.ready := true.B
*/
}
}
希望对您有所帮助!
我是新手,如果有人能解释一下作用:
1- 队列 2-解耦IO 3-解耦 3-有效IO 4- 有效
这段凿码正确吗?
...
val a = Decoupled()
val b = Decoupled()
val c = Decoupled()
...
val Reg_a = Reg(UInt())
val Reg_b = Reg(UInt())
...
when(io.a.valid && io.a.ready && io.b.valid && io.b.ready && io.c.valid && io.c.ready)
{
Reg_a := io.a.bits.data
Reg_b := io.b.bits.data
}
io.c.bits := Reg_a & Reg_b
...
Module.io.a <> Queue(Module_1.io.a_1)
Module.io.b <> Queue(Module_1.io.b_1)
Module_1.io.c_1 <> Queue(Module.io.c)
问候!
- Queue是一个硬件模块,它实现了一个先进先出的队列,带有DecoupledIO输入和输出
- DecoupledIO 是一个 ready/valid 接口类型,成员就绪、有效和位
- Decoupled 是从其他类型构造 DecoupledIO 的助手
- ValidIO 类似于DecoupledIO,只是它只有valid和bits
- Valid类似于Decoupled构造ValidIOs
我不知道代码试图做什么,但这是一个具有 2 个 DecoupledIO 输入和 1 个 DecoupledIO 输出的模块示例。它用队列缓冲输入,然后将输出连接到输入的总和:
import chisel3._
import chisel3.util._
class QueueModule extends Module {
val io = IO(new Bundle {
val a = Flipped(Decoupled(UInt(32.W))) // valid and bits are inputs
val b = Flipped(Decoupled(UInt(32.W)))
val z = Decoupled(UInt(32.W)) // valid and bits are outputs
})
// Note that a, b, and z are all of type DecoupledIO
// Buffer the inputs with queues
val qa = Queue(io.a) // io.a is the input to the FIFO
// qa is DecoupledIO output from FIFO
val qb = Queue(io.b)
// We only dequeue when io.z is ready
qa.nodeq() // equivalent to qa.ready := false.B
qb.nodeq()
// When qa and qb have valid inputs and io.z is ready for an output
when (qa.valid && qb.valid && io.z.ready) {
io.z.enq(qa.deq() + qb.deq())
/* The above is short for
io.z.valid := true.B
io.z.bits := qa.bits + qb.bits
qa.ready := true.B
qb.ready := true.B
*/
}
}
希望对您有所帮助!