双口ROM的Verilog代码

Question

我想编写双端口ROM 的verilog 代码以同时访问两个地址。我为单端口 ROM 编写了 verilog 代码，但无法为双端口 ROM 编写代码。

这是我的单端口 ROM verilog 代码。

always @(posedge clk)
 begin
   case(addr)
     3'b000:
     begin
     dout0<=9'b001001001;
     mod70<=001;
     mod50<=001;
     mod30<=001;
     end
     3'b001:
    begin
     dout1<=9'b010010010;
     mod71<=010;
     mod51<=001;
     mod31<=010;
     end
     3'b010:
    begin
     dout2<=9'b100100001;
     mod72<=100;
     mod52<=100;
     mod32<=001;
     end
     3'b011:
    begin
     dout3<=9'b001011010;
     mod73<=001;
     mod53<=011;
     mod33<=010;
     end
     3'b100: 
     begin
     dout4<=9'b010001001;
     mod74<=010;
     mod54<=001;
     mod34<=001;
     end
     3'b101:
    begin
     dout5<=9'b100010010;
     mod75<=100;
     mod55<=010;
     mod35<=010;
     end
     3'b110:
    begin
     dout6<=9'b001100001;
     mod76<=001;
     mod56<=100;
     mod36<=001;
     end
     3'b111:
    begin
     dout7<=9'b010011010;
     mod77<=010;
     mod57<=011;
     mod37<=010;
     end
     endcase
     end

Answer 1

在 Xilinx XST user guide 的第 147 页，您将找到 RAM 和 ROM 的示例。

他们没有提供双口ROM的例子，但是他们提供了双口RAM，你可以省略写成ROM：

此示例位于第 164 页：

module v_rams_11 (clk, a, dpra, spo, dpo);
    input   clk;               
    input   we;                
    input   [5:0] a;           
    input   [5:0] dpra;        
    output  [15:0] spo;        
    output  [15:0] dpo;        
    reg     [15:0] ram [63:0]; 
    reg     [5:0] read_a;      
    reg     [5:0] read_dpra;   

    always @(posedge clk) begin
        read_a <= a;
        read_dpra <= dpra;
    end

    assign spo = ram[read_a];
    assign dpo = ram[read_dpra];
endmodule

双口ROM的Verilog代码

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