输入变为零后如何保持相同的 FSM 状态？ (SystemVerilog)

Question

我正在尝试制作一个 FSM，它根据按下的按钮打开 LED 矩阵上的不同 LED。然而，LED 并没有保持亮起状态，松开按钮后，第一个 LED 再次亮起。这是代码：

module OneLed( input logic clk, reset, input logic [1:0] button, 
           output logic [7:0] rows, 
           output logic shcp, stcp, mr, oe, ds); //The LED matrix has 3 74hc595 shift registers below it

      logic [7:0] [23:0] in;
      logic [1:0] butreg; // thought a register would remember the button input
      assign butreg = button; 

      //FSM
      typedef enum logic [1:0] {S0, S1, S2} statetype;
      statetype state , nextstate;

     //state register
     always_ff @(posedge clk, posedge reset)
           if (reset) state <= S0;
           else state <= nextstate;

     //next state logic 
           always_comb
                 case(butreg)
                     S0: if (2'b01) nextstate = S1;
                         else if (2'b10) nextstate = S2;
                         else nextstate = S0;

                     S1: if (2'b01) nextstate = S2;
                         else if (2'b10) nextstate = S0;
                         else nextstate = S1;

                     S2: if (2'b01) nextstate = S0;
                         else if (2'b10) nextstate = S1;
                         else nextstate = S2;     
                     default: nextstate = S0;
           endcase 

    //output logic 
    always_comb
           begin
               if (state == S0)
                  in [0] = 24'b10000000_00000000_00000000;
               else if (state == S1)
                  in [0] = 24'b00000000_10000000_00000000;
               else  if (state == S2)        
                  in[0] =  24'b00000000_00000000_10000000;
   end         

   led LED ( clk, in , rows, shcp, stcp, mr, oe, ds); // this module works fine
endmodule

Answer 1

assign butreg = button;

此语句将 butreg 视为一根电线，直接连接到您的输入信号 button。

如果您希望将 button 的值锁存到寄存器 butreg 中，您需要使用总是在适当的事件（posedge clk 或 * 或其他一些条件）时阻止和触发。

例如，您可能有

而不是上面的赋值

always @(posedge clk) begin
  if (button == 2'b00) begin
    butreg <= butreg;
  end
  else begin
    butreg <= button;
  end
end

输入变为零后如何保持相同的 FSM 状态？ (SystemVerilog)

How to stay in the same FSM state after input turns zero? (SystemVerilog)

fsm

led

system-verilog