检查具有 +/- 容差百分比的时钟频率的最佳方法是什么？

Question

下面是我目前使用的属性

property freq_chk (time clk_period , bit disable_chk=0);
  time current_time; 
  disable iff ( disable_chk )
  ('1, current_time = $time) |=> 
   ( (($time - current_time) >= (clk_period-1)) && 
     (($time - current_time) <= (clk_period+1)) );
endproperty : freq_chk

所以我们在这里将时钟周期中的容差限制视为 +/-1。通过容差百分比并相应检查频率的最佳方法是什么。

我正在查看类似下面的内容（这不起作用，只是为了演示我正在查看的内容。）

property freq_chk_with_tol (time clk_period , bit disable_chk=0, int tolerance=0);
  time current_time; 
  disable iff ( disable_chk )
  ('1, current_time = $time) |=> 
   ( (($time - current_time) >= ( (clk_period * (1 - (tolerance/100) )) - 1)) && 
     (($time - current_time) <= ( (clk_period * (1 + (tolerance/100) )) + 1)) );
endproperty : freq_chk_with_tol

检查具有 +/- 容差 % 的时钟频率的最佳方法是什么？

Answer 1

正如 Greg 所建议的那样，将整数值更改为实数对我有用。

下面是工作代码。

property freq_chk_tol (time clk_period , bit disable_chk=0, real tolerance=0.00);
  time current_time; 
  disable iff ( disable_chk )
  ('1, current_time = $time) |=> 
   ( (($time - current_time) >= ( (clk_period * (1 - (tolerance/100.00) )) - 1)) && 
     (($time - current_time) <= ( (clk_period * (1 + (tolerance/100.00) )) + 1)) );
endproperty : freq_chk_tol

Answer 2

为什么要使用断言？使用行为代码不是更容易吗？

time clk_margin = <set it to whatever value you need>;   // calculate it once, don't calculate on the fly
time last_clk_tick;
always_ff @(posedge clk) begin
  assert (abs($time - last_clk_tick) < clk_margin);  // abs() is a user function return the absolute value
  last_clk_tick = $time;
end

检查具有 +/- 容差百分比的时钟频率的最佳方法是什么？

What would be the best method to check frequencies of clocks that has a +/- tolerance %?

system-verilog

uvm

system-verilog-assertions