rns减法的verilog代码

Question

我尝试编写用于执行模运算的 rns 减法的 verilog 代码。在下面给出的代码中，我输入 sum80 = 6'd4 sum81 = 6'd6 总和 30 = 6'd1 sum31 = 6'd4 sum71 = 6'd2 sum70 = 6'd3 sum50 = 6'd2 sum51 = 6'd1

但是根据这个 rad71= -1 和 rad51= -1，但是在模拟之后它给出了 rad71=rad51=1111111 这没问题但是在输出中 sum7x 应该等于（sum7x=6）和（sum5x=4 ) 但我得到 (sum5x=0000110) 和 (sum7x=0001000)

我希望它应该考虑 rad71=rad51= -1 和 sum5x= m5(7'd5)-rad51=4....如何得到这个.....我应该在我们的代码中做哪些更改

module mod_sub1(clk,rst,sum80,sum81,sum30,sum31,sum71,sum70,sum50,sum51,sum8x,sum3x,sum5x,sum7x,rad81,rad31,rad51,rad71);

parameter m3=6'b000011,m5=6'b000101,m7=6'b000111,m=13'd840,m8=6'b001000;
input clk;
input rst;
input [5:0] sum80,sum81,sum30,sum31,sum71,sum70,sum50,sum51;
output reg signed  [6:0] sum8x,sum3x,sum5x,sum7x;
 output reg  signed [6:0] rad81,rad31,rad51,rad71;


always@(posedge clk )
 begin
   rad81=sum81-sum80;
    if (rad81<0)
      sum8x=(m8-rad81);
     else 
      sum8x=rad81;
  end

 always@(posedge clk )
 begin
    rad31=sum31-sum30;
      if (rad81<0)
      sum3x=(m3-rad31);
     else 
      sum3x=rad31;
  end

   always@(posedge clk )
 begin
  rad71=sum71-sum70;
    if (rad71<0)
      sum7x=(m7-rad71);
     else 
      sum7x=rad71;
  end


 always@(posedge clk )
 begin
  rad51=sum51-sum50;
  if (rad51<0)
      sum5x=(m5-rad51);
     else 
      sum5x=rad51;
  end



endmodule

Answer 1

(rad31 mod 3) 是 rad31 +(-) 3，而不是 3 - rad31

rns减法的verilog代码

verilog code of rns subtraction

verilog

fpga

system-verilog