在 VLSI 中编译 VHDL 时出错

Question

我正在我的 VLSI 中创建一个 CPU，从寄存器开始：

library ieee;   
use ieee.std_logic_1164.all;

package types is
    type BYTE is array (7 downto 0) of std_logic;
end types;

-- Have to use one file because of Electric's compiler
library ieee;
use ieee.std_logic_1164.all; use work.types.all;

entity reg8 is
    port (
        clock   : in std_logic;
        inc     : in std_logic;
        dec     : in std_logic;
        store   : in std_logic;
        input   : in BYTE;
        output  : out BYTE
    );
end reg8;

architecture rtl of reg8 is
    signal state : BYTE;
begin
    tick : process(clock) is
    begin
        if(rising_edge(clock)) then
            if inc = '1' then
                state(0) <= not state(0);
                state(1) <= state(0) xor state(1);
                state(2) <= (state(0) and state(1)) xor state(2);
                state(3) <= (state(0) and state(1) and state(2)) xor state(3);
                state(4) <= (state(0) and state(1) and state(2) and state(3)) xor state(4);
                state(5) <= (state(0) and state(1) and state(2) and state(3) and state(4)) xor state(5);
                state(6) <= (state(0) and state(1) and state(2) and state(3) and state(4) and state(5)) xor state(6);
                state(7) <= (state(0) and state(1) and state(2) and state(3) and state(4) and state(5) and state(6)) xor state(7);
            elsif dec = '1' then
                state(0) <= not state(0);
                state(1) <= state(0) xnor state(1);
                state(2) <= (state(0) or state(1)) xnor state(2);
                state(3) <= (state(0) or state(1) or state(2)) xnor state(3);
                state(4) <= (state(0) or state(1) or state(2) or state(3)) xnor state(4);
                state(5) <= (state(0) or state(1) or state(2) or state(3) or state(4)) xnor state(5);
                state(6) <= (state(0) or state(1) or state(2) or state(3) or state(4) or state(5)) xnor state(6);
                state(7) <= (state(0) or state(1) or state(2) or state(3) or state(4) or state(5) or state(6)) xnor state(7);
            elsif store = '1' then
                state <= input;
            end if;
        end if;
        output <= state;
    end process tick;
end architecture rtl;

而且我遇到了我的语法检查器不会发生的奇怪错误，例如为什么我的进程需要 "PORT" 关键字。

来自 Electric 的完整日志：

Compiling VHDL in cell 'reg8{vhdl}' ...ERROR on line 25, Expecting keyword PORT:
tick : process(clock) is 
              ^
ERROR on line 25, Expecting keyword MAP:
tick : process(clock) is 
              ^
ERROR on line 25, Expecting a semicolon:
tick : process(clock) is 
                      ^
ERROR on line 26, Invalid ARCHITECTURAL statement:
begin 
^
ERROR on line 27, Expecting keyword END:
if(rising_edge(clock)) then 
^
ERROR on line 27, Expecting a semicolon:
if(rising_edge(clock)) then 
  ^
ERROR on line 27, No entry keyword - entity, architectural, behavioral:
if(rising_edge(clock)) then 
   ^
ERROR on line 27, No entry keyword - entity, architectural, behavioral:
if(rising_edge(clock)) then 
              ^
ERROR on line 27, No entry keyword - entity, architectural, behavioral:
if(rising_edge(clock)) then 
               ^
ERROR on line 27, No entry keyword - entity, architectural, behavioral:
if(rising_edge(clock)) then 
                    ^
ERROR on line 27, No entry keyword - entity, architectural, behavioral:
if(rising_edge(clock)) then 
                     ^
ERROR on line 27, No entry keyword - entity, architectural, behavioral:
if(rising_edge(clock)) then 
                       ^
ERROR on line 28, No entry keyword - entity, architectural, behavioral:
if inc = 11 then 
^
ERROR on line 28, No entry keyword - entity, architectural, behavioral:
if inc = 11 then 
   ^
ERROR on line 28, No entry keyword - entity, architectural, behavioral:
if inc = 11 then 
       ^
ERROR on line 28, No entry keyword - entity, architectural, behavioral:
if inc = 11 then 
         ^
ERROR on line 28, No entry keyword - entity, architectural, behavioral:
if inc = 11 then 
            ^
ERROR on line 29, No entry keyword - entity, architectural, behavioral:
state(0) <= not state(0); 
^
ERROR on line 29, No entry keyword - entity, architectural, behavioral:
state(0) <= not state(0); 
     ^
ERROR on line 29, No entry keyword - entity, architectural, behavioral:
state(0) <= not state(0); 
      ^
ERROR on line 29, No entry keyword - entity, architectural, behavioral:
state(0) <= not state(0); 
       ^
ERROR on line 29, No entry keyword - entity, architectural, behavioral:
state(0) <= not state(0); 
         ^
ERROR on line 29, No entry keyword - entity, architectural, behavioral:
state(0) <= not state(0); 
            ^
ERROR on line 29, No entry keyword - entity, architectural, behavioral:
state(0) <= not state(0); 
                ^
ERROR on line 29, No entry keyword - entity, architectural, behavioral:
state(0) <= not state(0); 
                     ^
ERROR on line 29, No entry keyword - entity, architectural, behavioral:
state(0) <= not state(0); 
                      ^
ERROR on line 29, No entry keyword - entity, architectural, behavioral:
state(0) <= not state(0); 
                       ^
ERROR on line 29, No entry keyword - entity, architectural, behavioral:
state(0) <= not state(0); 
                        ^
ERROR on line 30, No entry keyword - entity, architectural, behavioral:
state(1) <= state(0) xor state(1); 
^
TOO MANY ERRORS...PRINTING NO MORE

我正在使用 Electric VLSI，可在 http://www.staticfreesoft.com/index.html 获得，以防有人想尝试一下。

Answer 1

你问了，所以：

这似乎 "Electric" 不是通用的 VHDL 编译器。它只支持特定的子集和结构。 IE。你正在尝试做的事情可能不会奏效。您将需要切换到 "better"（付费）ASIC 综合工具，例如 Synopsys 工具。

使用传统晶体管实现由 ASIC 编译器制作的电路可能需要大量晶体管。它甚至可能无法按预期工作，因为 ASIC 设计程序大多需要非常特定的晶体管特性。只使用 (C)PLD 或一些逻辑门芯片（7400 系列）来实现您的设计会容易得多。

在 VLSI 中编译 VHDL 时出错

Error compiling VHDL in VLSI

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vhdl

vlsi