SV 中事件之间的时钟周期数

Question

我想计算信号的高值和低值之间的时钟周期数。我有一个信号 SIG，它在模拟过程中多次变高和变低。我想计算 high/low 时的平均周期数。

有人可以指导我如何实现吗it.Let我知道你是否需要更多说明。

Answer 1

你可以有一个时钟周期计数器，当信号SIG为高电平时开始计数，当SIG变低时停止计数，以测量时钟周期数而 SIG = "1":

int counter = 0; // counter initialization
@(posedge SIG); // waits for SIG to go high
while(SIG == 1) begin // while SIG = "1"
      @(posedge CLK); // when clock signal gets high
      counter++; // increase counter by 1
end

您可以在 SIG = "0" 和 @(negedge SIG); 时执行相同的操作。

Answer 2

您可以做的是计算每个值 high/low 的周期数，然后将它们放入队列中。然后在结束时将它们平均。

module top;
   bit sig, clk;

   int hiCount[$]={0}, loCount[$]={0};

   always #5 clk++;

   always @(negedge clk) // 5:1 chance of keeping the same value
     randomize(sig) with {sig == const'(sig) dist { 1 := 5, 0 := 1 }; };

   always @(posedge clk) begin
      case(sig)
    1: if ($stable(sig))
      hiCount[$]++;
    else
      hiCount.push_back(1); // first cycle high
    0: if ($stable(sig))
      loCount[$]++;
    else
      loCount.push_back(1); // first cycle low
      endcase // case (sig)
      $display("sig: %0d\nhi:%p\nlo: %p",sig,hiCount,loCount);
      end
   initial begin
      repeat(100) @(posedge clk);
      if (loCount[0] == 0) void'(loCount.pop_front());
      if (hiCount[0] == 0) void'(hiCount.pop_front());

      $display("sig was high %0d times with average cycle count of %0d",
           hiCount.size(), hiCount.sum()/hiCount.size);
            $display("sig was low %0d times with average cycle count of %0d",
           loCount.size(), loCount.sum()/loCount.size);
      $finish;
   end
endmodule // top

SV 中事件之间的时钟周期数

Number of Clock Cycles between events in SV

system-verilog

clock