凿子模块接线顺序

Question

我正在关注这里的答案：。我有一个问题，关于如何处理 Seq 中的 previus 项目。这是我的代码：

val ccfLinks = for (j <- 0 until (len - 1)) yield {
   val exe_unit = Module(new Ccflink(bitwidth))
      if (j == 0) { 
        // connnect the first stage //
        exe_unit.io.i_in := io.i_in
        exe_unit.io.q_in := io.q_in
        exe_unit.io.coeff_i := coeffs_i(0)
        exe_unit.io.coeff_q := coeffs_q(0)
        exe_unit.io.pre_i_product := SInt(0)
        exe_unit.io.pre_q_product := SInt(0)
    } else {
        // connect the rest of the chain //
        exe_unit.io.i_in := ccfLinks(j-1).io.i_out
        exe_unit.io.q_in := ccfLinks(j-1).io.q_out
        exe_unit.io.coeff_i := coeffs_i(j)
        exe_unit.io.coeff_q := coeffs_q(j)
        exe_unit.io.pre_i_product := ccfLinks(j-1).io.i_product
        exe_unit.io.pre_q_product := ccfLinks(j-1).io.q_product
    }
    exe_unit
}

我正在尝试将当前模块连接到前一个模块，如何定位前一个模块？尝试编译上面的代码会导致下一个错误：

"Ccf.scala:240: recursive value ccfLinks needs type [error] exe_unit.io.i_in := ccfLinks(j-1).io.i_out"

Answer 1

这是一种相当直接的方法。请注意 foldLeft 的使用，它采用列表的头部并使用连续的对调用代码 thunk。使用更高级的列表理解可以使它更简洁一些，但我认为这很清楚什么时候发生了什么。

class Element extends Module {
  val io = IO(new Bundle {
    val in0 = Input(UInt(8.W))
    val in1 = Input(UInt(8.W))
    val out0 = Output(UInt(8.W))
    val out1 = Output(UInt(8.W))
  })

  val reg0 = RegNext(io.in0, 0.U)
  val reg1 = RegNext(io.in1, 0.U)

  io.out0 := reg0
  io.out1 := reg1
}

/**
  * wire together a bunch of elements, into a basic queue
  * @param elementCount how big is the queue
  */
class ElementQueue(val elementCount: Int) extends Module {
  val io = IO(new Bundle {
    val in0 = Input(UInt(8.W))
    val in1 = Input(UInt(8.W))
    val out0 = Output(UInt(8.W))
    val out1 = Output(UInt(8.W))
  })

  // create a scala Seq of Elements
  val elements = Seq.fill(elementCount)(Module(new Element))

  // wire the head to the inputs
  elements.head.io.in0 := io.in0
  elements.head.io.in1 := io.in1

  // wire the elements of the queue
  val last = elements.tail.foldLeft(elements.head) { case (prior, next) =>
    next.io.in0 := prior.io.out0
    next.io.in1 := prior.io.out1
    next
  }

  // wire the end of the queue to the outputs
  io.out0 := last.io.out0
  io.out1 := last.io.out1
}

凿子模块接线顺序

Wiring Seq of chisel modules

chisel