在 Chisel 中实现 Verilog $onehot 任务
Implement a Verilog $onehot task in Chisel
是否有直接的方法来检查 Chisel 中的 1-hot 总线编码?
我目前的解决方案似乎有点难看。我可以做得更好吗?
val range = Output (Vec (num, Bool()))
val outSum = io.range map ( p => if ( p == true.B ) 1.U else 0.U ) reduceleft (_ + _)
// This is $onehot0
assert (outSum <= 1.U, "One-hot0 bus encoding failed")
// This is $onehot
assert (outSum == 1.U, "One-hot bus encoding failed")
你可以使用 PopCount
import chisel3._
import chisel3.util.PopCount
...
val io = IO(new Bundle {
val range = Output(Vec(num, Bool()))
})
val outSum = PopCount(io.range)
// assertions...
是否有直接的方法来检查 Chisel 中的 1-hot 总线编码?
我目前的解决方案似乎有点难看。我可以做得更好吗?
val range = Output (Vec (num, Bool()))
val outSum = io.range map ( p => if ( p == true.B ) 1.U else 0.U ) reduceleft (_ + _)
// This is $onehot0
assert (outSum <= 1.U, "One-hot0 bus encoding failed")
// This is $onehot
assert (outSum == 1.U, "One-hot bus encoding failed")
你可以使用 PopCount
import chisel3._
import chisel3.util.PopCount
...
val io = IO(new Bundle {
val range = Output(Vec(num, Bool()))
})
val outSum = PopCount(io.range)
// assertions...