队列声明 SystemVerilog 编译错误

Question

您好，我在使用 Intel Quartus Prime 的 SystemVerilog 文件中的测试台模块中有下一行代码：

`timescale 1ns/1ps

 module fo;

    parameter retardo_reset = 150;
    parameter repetir = 2;

    reg clock;
    reg reset;
    reg clear;
    reg rden;
    reg wren;
    reg [7:0] data_in;
    reg [7:0] data_out;
    reg [7:0] queue [$:31];             
    reg [7:0] random_number;

    wire aempty;
    wire afull;
    wire empty;
    wire full;

    // There is more code there ...

但是编译器说在 声明队列的行 reg [7:0] queue [$:31]; 有下一个错误：

Error (10170): Verilog HDL syntax error at fo.sv(15) near text: "$"; expecting an operand. Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.

你知道我做错了什么吗？因为这是在 SystemVerilog 中声明有限队列的正确方法。

Answer 1

根据Quartus manual，它目前不支持队列数据类型的合成，即使有界。

队列声明 SystemVerilog 编译错误

Queue declaration SystemVerilog compiling error

queue

system-verilog

quartus