Modelsim 中 wait_order 的问题 - 意外的关键字

Question

我正在尝试运行在 Modelsim 中从 chipverify 网站获取一些代码，但它不起作用 - 我不知道为什么。来自网站的例子是关于 wait_order.

module tb;
  // Declare three events that can be triggered separately
  event a, b, c;

  // This block triggers each event one by one
  initial begin
    #10 -> a;
    #10 -> b;
    #10 -> c;
  end

  // This block waits until each event is triggered in the given order
  initial begin

    wait_order (a,b,c) 
      $display ("Events were executed in the correct order");
    else 
        $display ("Events were NOT executed in the correct order !");  
  end
endmodule

我期望输出：

Events were executed in the correct order.

但是我得到了这样的结果：

syntax error, unexpected "SystemVerilog keyword 'wait_order'"

Answer 1

这是 SystemVerilog 在 Modelsim 中未实现的功能。检查文档。

带断言的 SystemVerilog sequences 为您提供许多相同的功能。

Modelsim 中 wait_order 的问题 - 意外的关键字

Problem with wait_order in Modelsim - unexpected keyword

system-verilog

modelsim