Systemverilog Vivado 中的增量操作未按预期工作

Question

Sum：状态机名为“WaitS2”的部分仅递增“count”一次。

我正在尝试控制 systemverilog 中的超声波传感器 HC-SR04。正如我在数据表中看到的那样，该传感器创建一个信号“trigger”，该信号会创建声音，并在生成声音传感器后创建逻辑“echo” ，我需要计算时间，以便创建您可以在代码中看到的状态机，但问题是 count++ 没有像预期的那样工作，无论回声信号有多长，它只递增计数变量一次

我使用了另一个来自互联网的名为32位加法器的模块，它没有改变任何东西。我将所有语句更改为非块语句，但它不起作用。我什至尝试将 count++ 更改为 count = count + 1 没有用

module sensorFSM(
    input logic echo , clk ,reset, 
    output logic trig,
    output logic[31:0] distance,
    output logic[1:0] presentState
    );
    /*typedef enum logic[1:0] {BeginS , WaitS , ReturnS } states;
    states presentState , nextState;
    */
    logic[31:0] count , count1; 
    logic[1:0] BeginS , WaitS, WaitS2 , ReturnS  , nextState;
    assign BeginS = 2'b00;
    assign WaitS = 2'b01; 
    assign WaitS2 = 2'b10;
    assign ReturnS = 2'b11; 

    // clk and state change
    always_ff @( posedge clk )
        begin
            if ( reset == 1'b1 )
            presentState <= BeginS;
            else
            presentState <= nextState;
        end

    // real state changes    
    always_comb 
        begin            
            case(presentState)           
            BeginS:
                begin
                    trig = 1'b1;
                    count = 32'b0;
                    nextState = WaitS;
                end
            WaitS:
                begin
                    trig = 1'b0;
                    distance = 32'b0;
                    //#5000;
                    nextState = WaitS2;
                end
            WaitS2:
                begin
                    if( echo  == 1 )
                      begin
                        if ( count < 24'b101100111000000100100000 )
                            begin 
                            // here is the problem count is only incrementing 
                            //once
                                count++;                               
                                nextState = WaitS2; 
                            end 
                         else 
                            begin
                                distance = count;
                                nextState = BeginS;
                            end 
                      end
                    else // echo == 0   
                        begin
                            nextState = ReturnS;
                        end
                   end 
            ReturnS:
                begin
                    //count =  count / 1470;
                    distance = count;
                    nextState = BeginS;
                end
            default:
                nextState = BeginS;
            endcase
         end  
endmodule

我预计模拟会计数大约 1 百万，但它始终输出 1，但我可以看到当 echo 也处于活动状态时，名为 "WaitS2" 的状态会持续很长时间

Answer 1

您在 always_comb 内创建了 count++; 的异步反馈循环。您需要使 count 成为一个寄存器。

另外 trig 和 distance 目前推断为 level-sensitive 个闩锁。 distance 需要失败。 trig 可以写成纯组合逻辑，但由于它是一个输出，我强烈建议将其设为触发器以消除输出毛刺的上升。

always_ff @( posedge clk )
    begin
      if ( reset == 1'b1 ) begin
        presentState <= BeginS;
        trig <= 0; // <-- reset
        distance <= 0; // <-- reset
        count <= 0; // <-- reset
      end else begin
        presentState <= nextState;
        trig <= next_trig; // <-- flop trig
        distance <= next_distance; // <-- flop distance
        count <= next_count; // <-- flop count
      end
    end

// real state changes    
always_comb 
    begin
      next_trig = trig; // <-- default value is flopped value
      next_distance = distance; // <-- default value is flopped value
      next_count = count; // <-- default value is flopped value
        case(presentState)           
        BeginS:
            begin
                //trig = 1'b1; // <-- is now a flop assigned in always_ff
                //count = 32'b0; // <-- is now a flop assigned in always_ff
                next_trig = 1'b1; // <-- update value
                next_count = 32'b0; // <-- update value
                nextState = WaitS;
            end
        WaitS:
            // ... replace trig/distance with next_trig/next_distance in here ...
        WaitS2:
            begin
              // ...
              //count++;  // <-- NOPE would be asynchronous feedback
              next_count = count + 1; // <-- synchronous increment
              // ...
            end
        ReturnS:
            //  ... replace distance with next_distance in here ...
        default:
            nextState = BeginS;
        endcase
     end

Systemverilog Vivado 中的增量操作未按预期工作

increment operation in Systemverilog Vivado not working as expected

verilog

system-verilog

vivado