系统 Verilog 错误,GPIO_0 不是函数
System Verilog Error , GPIO_0 is not a function
我有一个这样的模块
module DE1_SoC (CLOCK_50, HEX0, HEX1, HEX2, HEX3, SW, GPIO, KEY);
input CLOCK_50; // 50MHz clock.
output reg [6:0] HEX0;
output reg [6:0] HEX1;
output reg [6:0] HEX2;
output reg [6:0] HEX3;
inout [35:0] GPIO;
input [9:0] SW;
input [4:0] KEY;
control_top U_control_top(
start(SW[0]),
reset(SW[1]),
clock(CLOCK_50),
controller(~KEY[0]),
GPIO(GPIO_0[35:0]),
out_1(HEX0),
out_2(HEX1),
out_3(HEX2),
out_4(HEX3)
);
而且我一直收到一个名为:
的错误
Error (10153): Verilog HDL Function Call or Function Declaration error
at DE1_SoC.sv(17): identifier "GPIO" is not a function
而我的control_top模块是这样的
module control_top(
input start,
input reset,
input clock,
//=========connect to bird_controller=====
input controller,
//========connect to led_matrix=====
inout [35:0] GPIO_0,
//====connect to HEX================
output [6:0] out_1,
output [6:0] out_2,
output [6:0] out_3,
output [6:0] out_4
);
按名称实例化模块端口时,需要在每个信号名称前添加一个点(.
):
control_top U_control_top(
.start(SW[0]),
.reset(SW[1]),
.clock(CLOCK_50),
.controller(~KEY[0]),
.GPIO_0(GPIO_0[35:0]),
.out_1(HEX0),
.out_2(HEX1),
.out_3(HEX2),
.out_4(HEX3)
);
我有一个这样的模块
module DE1_SoC (CLOCK_50, HEX0, HEX1, HEX2, HEX3, SW, GPIO, KEY);
input CLOCK_50; // 50MHz clock.
output reg [6:0] HEX0;
output reg [6:0] HEX1;
output reg [6:0] HEX2;
output reg [6:0] HEX3;
inout [35:0] GPIO;
input [9:0] SW;
input [4:0] KEY;
control_top U_control_top(
start(SW[0]),
reset(SW[1]),
clock(CLOCK_50),
controller(~KEY[0]),
GPIO(GPIO_0[35:0]),
out_1(HEX0),
out_2(HEX1),
out_3(HEX2),
out_4(HEX3)
);
而且我一直收到一个名为:
的错误Error (10153): Verilog HDL Function Call or Function Declaration error at DE1_SoC.sv(17): identifier "GPIO" is not a function
而我的control_top模块是这样的
module control_top(
input start,
input reset,
input clock,
//=========connect to bird_controller=====
input controller,
//========connect to led_matrix=====
inout [35:0] GPIO_0,
//====connect to HEX================
output [6:0] out_1,
output [6:0] out_2,
output [6:0] out_3,
output [6:0] out_4
);
按名称实例化模块端口时,需要在每个信号名称前添加一个点(.
):
control_top U_control_top(
.start(SW[0]),
.reset(SW[1]),
.clock(CLOCK_50),
.controller(~KEY[0]),
.GPIO_0(GPIO_0[35:0]),
.out_1(HEX0),
.out_2(HEX1),
.out_3(HEX2),
.out_4(HEX3)
);