如何识别同步复位(在 verilog 中)
How to identify synchronous resets (in verilog)
我是 EDA 新手,我有以下 verilog 代码,我需要清楚地识别同步复位。
module test(clk,d,rst,a);
input clk,d,rst;
output reg a;
always @(posedge clk)
begin
if(rst)
a <= 1'b0;
else
a <= 1'b1; // assigned to a constant
end
endmodule
'rst' 是重置(同步)吗?
以下是您使用同步和异步重置的代码。
//Synchronous Reset
module test(clk,d,rst,a);
input clk,d,rst;
output reg a;
always @(posedge clk) //This clock makes the reset synchronized to a clock signal.
begin
if(rst)
a <= 1'b0;
else
a <= 1'b1; // assigned to a constant
end
endmodule
//Asynchronous
module test(clk,d,rst,a);
input clk,d,rst;
output reg a;
always @* //No clock to synchronize with.
begin //Reset signal will drive anytime a input value changes
if(rst)
a <= 1'b0;
else
a <= 1'b1; // assigned to a constant
end
endmodule
接受的答案是错误的,因为第二个代码示例实际上是一个组合代码,根本不使用时钟,我们需要实现一个顺序代码。
第一个代码示例是同步复位:
//Synchronous Reset
module test(clk,d,rst,a);
input clk,d,rst;
output reg a;
always @(posedge clk)
begin
if(rst) // In order to execute this line, clk and reset both have to be in posedge.
a <= 1'b0;
else
a <= 1'b1; // assigned to a constant
end
endmodule
第二个代码示例是异步重置:
//Asynchronous Reset
module test(clk,d,rst,a);
input clk,d,rst;
output reg a;
always @(posedge clk, posedge rst)
begin
if(rst) // In order to execute this line, rst has to be in posedge(clk's value doesn't
// matter here, it can be either posedge or negedge, what's important is rst's value).
a <= 1'b0;
else
a <= 1'b1; // assigned to a constant
end
endmodule
我是 EDA 新手,我有以下 verilog 代码,我需要清楚地识别同步复位。
module test(clk,d,rst,a);
input clk,d,rst;
output reg a;
always @(posedge clk)
begin
if(rst)
a <= 1'b0;
else
a <= 1'b1; // assigned to a constant
end
endmodule
'rst' 是重置(同步)吗?
以下是您使用同步和异步重置的代码。
//Synchronous Reset
module test(clk,d,rst,a);
input clk,d,rst;
output reg a;
always @(posedge clk) //This clock makes the reset synchronized to a clock signal.
begin
if(rst)
a <= 1'b0;
else
a <= 1'b1; // assigned to a constant
end
endmodule
//Asynchronous
module test(clk,d,rst,a);
input clk,d,rst;
output reg a;
always @* //No clock to synchronize with.
begin //Reset signal will drive anytime a input value changes
if(rst)
a <= 1'b0;
else
a <= 1'b1; // assigned to a constant
end
endmodule
接受的答案是错误的,因为第二个代码示例实际上是一个组合代码,根本不使用时钟,我们需要实现一个顺序代码。 第一个代码示例是同步复位:
//Synchronous Reset
module test(clk,d,rst,a);
input clk,d,rst;
output reg a;
always @(posedge clk)
begin
if(rst) // In order to execute this line, clk and reset both have to be in posedge.
a <= 1'b0;
else
a <= 1'b1; // assigned to a constant
end
endmodule
第二个代码示例是异步重置:
//Asynchronous Reset
module test(clk,d,rst,a);
input clk,d,rst;
output reg a;
always @(posedge clk, posedge rst)
begin
if(rst) // In order to execute this line, rst has to be in posedge(clk's value doesn't
// matter here, it can be either posedge or negedge, what's important is rst's value).
a <= 1'b0;
else
a <= 1'b1; // assigned to a constant
end
endmodule