Verilog 测试平台未正确读取测试向量

Question

我正在编写 SystemVerilog 测试平台来测试 4 输入 XOR 函数。我已经检查以确保没有错误，但不知何故测试台没有正确读取测试向量文件。

谁能告诉我我做错了什么？

  module testbench_xor();
    logic clk, reset;
    logic [3:0] a, yexpected;
  logic y;
  logic [31:0] vectornum, errors; // bookkeeping variables
  logic [4:0] testvectors[0:10000]; // array of testvectors

  // instantiate device under test
  xor_4 dut({a[3:0]}, y);

  // generate clock
  always
    begin
      clk = 1; #5; clk = 0; #5;
    end

  // load vectors at start of test and
  // pulse reset
  initial
    begin
      $readmemb("test3.tv", testvectors);
      vectornum = 0; errors = 0;
      reset = 1; #27; reset = 0;
    end

  // apply test vectors at rising edge of clock
  always @(posedge clk)
    begin
      #1; {a[3:0], yexpected} = testvectors[vectornum];
    end

  // check results
  always @(negedge clk)
    if (~reset) begin
      if (y !== yexpected) begin
        $display("Error: inputs = %b", a[3:0]);
        $display(" outputs = %b (%b expected)",y,yexpected);
        errors = errors + 1;
      end

    vectornum = vectornum + 1;
    if (testvectors[vectornum] === 5'bx) begin
      $display("%d tests completed with %d errors", vectornum, errors);
      $finish;
    end
   end
  endmodule

test3.tv

ModelSim 成绩单

# Compile of xor.sv was successful.
# Compile of testbench_xor.sv was successful.
# 2 compiles, 0 failed with no errors.
vsim -gui work1.testbench_xor
# vsim 
# Start time: 02:22:26 on Nov 22,2019
# Loading sv_std.std
# Loading work1.testbench_xor
# Loading work1.xor_4
add wave -position end  sim:/testbench_xor/clk
add wave -position end  sim:/testbench_xor/reset
add wave -position end  sim:/testbench_xor/a
add wave -position end  sim:/testbench_xor/yexpected
add wave -position end  sim:/testbench_xor/y
add wave -position end  sim:/testbench_xor/vectornum
add wave -position end  sim:/testbench_xor/errors
add wave -position end  sim:/testbench_xor/testvectors
run -all
# Error: inputs = 0000
#  outputs = 0 (0011 expected)
# Error: inputs = 0000
#  outputs = 0 (0101 expected)
# Error: inputs = 0000
#  outputs = 0 (0110 expected)
# Error: inputs = 0000
#  outputs = 0 (1001 expected)
# Error: inputs = 0000
#  outputs = 0 (1010 expected)
# Error: inputs = 0000
#  outputs = 0 (1100 expected)
# Error: inputs = 0000
#  outputs = 0 (1111 expected)
# Error: inputs = 0001
#  outputs = 1 (0010 expected)
# Error: inputs = 0001
#  outputs = 1 (0100 expected)
# Error: inputs = 0001
#  outputs = 1 (0111 expected)
# Error: inputs = 0001
#  outputs = 1 (1000 expected)
# Error: inputs = 0001
#  outputs = 1 (1011 expected)
# Error: inputs = 0001
#  outputs = 1 (1101 expected)
# Error: inputs = 0001
#  outputs = 1 (1110 expected)
#         16 tests completed with         14 errors
# ** Note: $finish    : C:/Modeltech_pe_edu_10.4a/examples/testbench_xor.sv(39)
#    Time: 185 ns  Iteration: 1  Instance: /testbench_xor
# 1
# Break in Module testbench_xor at C:/Modeltech_pe_edu_10.4a/examples/testbench_xor.sv line 39

截图

我在网上发现了另一个类似的问题，并且我已经用 question/answer 交叉检查了我的代码。但是，我似乎仍然无法弄清楚我做错了什么。

Answer 1

您声明 yexpected 为 4 位宽（如您的 wave 所示，4'he），但您希望它为 1 位宽。

变化：

  logic [3:0] a, yexpected;

收件人：

  logic [3:0] a;
  logic yexpected;

加载 testvectors 工作正常，但读取不正常。

Verilog 测试平台未正确读取测试向量

Verilog testbench not reading test vector correctly

verilog

system-verilog

testbed

test-bench