有没有办法让 Chisel 中未在模块范围内定义的信号在波形中可见?

Is there a way to make signals in Chisel not defined at module scope visible in waveforms?

如果我们以下面的代码摘录(在模块的顶部)为例:

val write_indices = WireInit(VecInit(Seq.fill(wordsPerBeat)(0.U((log2Ceil(nWays)+log2Ceil(nSets)+log2Ceil(cacheBlockBytes/wordBytes)).W))))
val write_line_indices = WireInit(VecInit(Seq.fill(wordsPerBeat)(0.U(log2Ceil(cacheBlockBytes/wordBytes).W))))
dontTouch(write_indices)
dontTouch(write_line_indices)
// refill logic
when(mem_response_present) {
  for (i <- 0 until wordsPerBeat) {
    val beatIdx = i.U(log2Ceil(wordsPerBeat).W)
    val write_line_index = Cat(d_refill_cnt(log2Ceil(cacheBlockBytes/wordsPerBeat/wordBytes)-1, 0), beatIdx)
    val write_idx = Cat(refill_way, refill_set, write_line_index)
    write_indices(i) := write_idx
    write_line_indices(i) := write_line_index
    cache_line(write_idx) := tl_out.d.bits.data((i + 1) * wordBits - 1, i * wordBits)
  }
}

两个顶级信号的唯一原因是为了让较低的信号在波形中可见。 有什么方法可以达到相同的效果而无需手动创建这些信号? 在此示例中,一半代码仅用于获得调试能力。 好像有点过分了。

That seems a bit excessive

完全同意,幸好有解决办法。出于实施原因,默认情况下,Chisel 只能命名模块 class 的 public 字段。也就是说,只有模块顶级范围内的值。然而,有一个漂亮的宏 chisel3.experimental.chiselName 可以 for 循环中命名这些值。尝试像这样注释您的模块:

import chisel3._
import chisel3.experimental.chiselName

@chiselName
class MyModule extends Module {
  ...
}

请查看 this earlier answer discussing naming,它提供的信息比单独回答这个问题的相关信息更多,但它还有其他关于 Chisel 中命名工作原理的有用信息。