这个语法在 chisel 中是如何解释的？

Question

我正在学习凿子和火箭芯片。我最近在 rocket / RocketCore.scala 文件中发现了一个不可读的语法。

val perfEvents = new EventSets(Seq(
new EventSet((mask, hits) => Mux(mask(0), wb_xcpt, wb_valid && pipelineIDToWB((mask & hits).orR)), Seq(
  ("exception", () => false.B),
  ("load", () => id_ctrl.mem && id_ctrl.mem_cmd === M_XRD && !id_ctrl.fp),
  ("store", () => id_ctrl.mem && id_ctrl.mem_cmd === M_XWR && !id_ctrl.fp),
  ("amo", () => Bool(usingAtomics) && id_ctrl.mem && (isAMO(id_ctrl.mem_cmd) || id_ctrl.mem_cmd.isOneOf(M_XLR, M_XSC))),
  ("system", () => id_ctrl.csr =/= CSR.N),
  ("arith", () => id_ctrl.wxd && !(id_ctrl.jal || id_ctrl.jalr || id_ctrl.mem || id_ctrl.fp || id_ctrl.mul || id_ctrl.div || id_ctrl.csr =/= CSR.N)),
  ("branch", () => id_ctrl.branch),
  ("jal", () => id_ctrl.jal),
  ("jalr", () => id_ctrl.jalr))
  ++ (if (!usingMulDiv) Seq() else Seq(
    ("mul", () => if (pipelinedMul) id_ctrl.mul else id_ctrl.div && (id_ctrl.alu_fn & ALU.FN_DIV) =/= ALU.FN_DIV),
    ("div", () => if (pipelinedMul) id_ctrl.div else id_ctrl.div && (id_ctrl.alu_fn & ALU.FN_DIV) === ALU.FN_DIV)))
  ++ (if (!usingFPU) Seq() else Seq(
    ("fp load", () => id_ctrl.fp && io.fpu.dec.ldst && io.fpu.dec.wen),
    ("fp store", () => id_ctrl.fp && io.fpu.dec.ldst && !io.fpu.dec.wen),
    ("fp add", () => id_ctrl.fp && io.fpu.dec.fma && io.fpu.dec.swap23),
    ("fp mul", () => id_ctrl.fp && io.fpu.dec.fma && !io.fpu.dec.swap23 && !io.fpu.dec.ren3),
    ("fp mul-add", () => id_ctrl.fp && io.fpu.dec.fma && io.fpu.dec.ren3),
    ("fp div/sqrt", () => id_ctrl.fp && (io.fpu.dec.div || io.fpu.dec.sqrt)),
    ("fp other", () => id_ctrl.fp && !(io.fpu.dec.ldst || io.fpu.dec.fma || io.fpu.dec.div || io.fpu.dec.sqrt))))),
new EventSet((mask, hits) => (mask & hits).orR, Seq(
  ("load-use interlock", () => id_ex_hazard && ex_ctrl.mem || id_mem_hazard && mem_ctrl.mem || id_wb_hazard && wb_ctrl.mem),
  ("long-latency interlock", () => id_sboard_hazard),
  ("csr interlock", () => id_ex_hazard && ex_ctrl.csr =/= CSR.N || id_mem_hazard && mem_ctrl.csr =/= CSR.N || id_wb_hazard && wb_ctrl.csr =/= CSR.N),
  ("I$ blocked", () => icache_blocked),
  ("D$ blocked", () => id_ctrl.mem && dcache_blocked),
  ("branch misprediction", () => take_pc_mem && mem_direction_misprediction),
  ("control-flow target misprediction", () => take_pc_mem && mem_misprediction && mem_cfi && !mem_direction_misprediction && !icache_blocked),
  ("flush", () => wb_reg_flush_pipe),
  ("replay", () => replay_wb))
  ++ (if (!usingMulDiv) Seq() else Seq(
    ("mul/div interlock", () => id_ex_hazard && (ex_ctrl.mul || ex_ctrl.div) || id_mem_hazard && (mem_ctrl.mul || mem_ctrl.div) || id_wb_hazard && wb_ctrl.div)))
  ++ (if (!usingFPU) Seq() else Seq(
    ("fp interlock", () => id_ex_hazard && ex_ctrl.fp || id_mem_hazard && mem_ctrl.fp || id_wb_hazard && wb_ctrl.fp || id_ctrl.fp && id_stall_fpu)))),
new EventSet((mask, hits) => (mask & hits).orR, Seq(
  ("I$ miss", () => io.imem.perf.acquire),
  ("D$ miss", () => io.dmem.perf.acquire),
  ("D$ release", () => io.dmem.perf.release),
  ("ITLB miss", () => io.imem.perf.tlbMiss),
  ("DTLB miss", () => io.dmem.perf.tlbMiss),
  ("L2 TLB miss", () => io.ptw.perf.l2miss)))))

使用classEventSet时，没有找到mask和hits的定义

Answer 1

mask 和 hits 只是传递给 EventSet 构造函数的 lambda 参数，(mask, hits) => ... 部分是他们的定义（或声明，如果你愿意的话）。如果您查看 EventSet source，您可以看到 lambda 被称为 gate 并且仅在该方法中使用：

def check(mask: UInt) = gate(mask, hits)

所以 mask 将是 check 的参数，而 hits 来自

def hits = events.map(_._2()).asUInt

在这种情况下，第一个 EventSet 你会得到类似

Seq(
  false.B,
  id_ctrl.mem && id_ctrl.mem_cmd === M_XRD && !id_ctrl.fp,
  ...
).asUInt

Answer 2

这是一段相当吓人的代码。分解

perfEvents 被指定为 EventSets
EventSets需要一个参数
- class EventSets(val eventSets: Seq[EventSet])
- 因此您看到 Seq 个 EventSet 开始创建。
EventSet需要两个参数
- class EventSet(gate: (UInt, UInt) => Bool, events: Seq[(String, () => Bool)])
- 第一个：两个UInts的函数，即returns一个Bool
- 第二个：String 的 2 个元组的 Seq 和一个没有参数的函数 returns a Bool
- 因此您会看到定义了这些元组的长序列。
- 注意：(String, () => Bool()) 的顺序需要根据配置参数的不同而不同，例如 usingMulDiv
  - 因此您多次看到结构 ++ (if (..。
  - 这使用 if 有条件地将元组的不同子序列添加到它正在构造的 EventSet 参数中。

希望对您有所帮助。这是一大堆东西，可能要么丑陋而简短，要么更清晰、非常冗长和冗长。通过格式化程序可能会对运行有一点帮助。这是其中的一点。

val perfEvents = new EventSets(
  Seq(
    new EventSet(
      (mask, hits) => Mux(wb_xcpt, mask(0), wb_valid && pipelineIDToWB((mask & hits).orR)),
      Seq(
        ("exception", () => false.B),
        ("load", () => id_ctrl.mem && id_ctrl.mem_cmd === M_XRD && !id_ctrl.fp),
        ("store", () => id_ctrl.mem && id_ctrl.mem_cmd === M_XWR && !id_ctrl.fp),
        ("amo",
         () =>
           Bool(usingAtomics) && id_ctrl.mem && (isAMO(id_ctrl.mem_cmd) || id_ctrl.mem_cmd.isOneOf(M_XLR, M_XSC))),
        ("system", () => id_ctrl.csr =/= CSR.N),
        ("arith",
         () =>
           id_ctrl.wxd && !(id_ctrl.jal || id_ctrl.jalr || id_ctrl.mem || id_ctrl.fp || id_ctrl.mul || id_ctrl.div || id_ctrl.csr =/= CSR.N)),
        ("branch", () => id_ctrl.branch),
        ("jal", () => id_ctrl.jal),
        ("jalr", () => id_ctrl.jalr)
      )
        ++ (if (!usingMulDiv) Seq()
            else
              Seq(

这个语法在 chisel 中是如何解释的？

How is this syntax explained in chisel?

scala

chisel

rocket-chip