VHDL 到 Verilog

Question

我有一些 VHDL 代码正在尝试转换为 Verilog。

VHDL 代码工作正常

library ieee;                                
use ieee.std_logic_1164.all;                 
                                             
entity find_errors is port(                      
    a: bit_vector(0 to 3);                   
    b: out std_logic_vector(3 downto 0);         
    c: in bit_vector(5 downto 0));            
end find_errors;                            
                                             
architecture not_good of find_errors is        
  begin                                      
  my_label: process (a,c)                         
    begin                                    
    if c = "111111" then                                
      b <= To_StdLogicVector(a);                                
    else                                     
     b <= "0101";                            
    end if;                                   
  end process;                              
end not_good;                                 

我的 Verilog 代码出现错误“对网络“bw”的非法引用。” 和 连续赋值左边寄存器不合法

module find_errors(                            
  input  [3:0]a,                             
  output [3:0]b,                             
  input [5:0]c                               
);                                            
  wire [0:3]aw;                              
  wire [3:0]bw;                             
  reg [5:0]creg;                              
                                       
  assign aw = a;                             
  assign b = bw;                             
  assign creg = c;                          
always @(a,c)                                      
  begin                                      
    if (creg == 4'b1111)   
       bw <= aw;                              
    else                                     
     bw <= 4'b0101;                            
    end                                                          
endmodule 

Answer 1

aw和creg是不必要的，bw需要声明为reg。

module find_errors(
  input  [3:0] a,
  output [3:0] b,
  input [5:0] c
);
                                                   
reg [3:0] bw;
assign b = bw;

always @(a,c)
begin
  if (c == 4'b1111)
    bw <= a;
  else
    bw <= 4'b0101;
end

endmodule

因为没有顺序逻辑，你甚至不需要 always 块：

module find_errors(
  input  [3:0] a,
  output [3:0] b,
  input [5:0] c
);
                                                   
assign b = (c == 4'b1111) ? a : 4'b0101;

endmodule

Answer 2

看起来很接近，但有一些东西 problems/errors 需要修复，请参阅修复代码中的内联注释：

module find_errors(                            
  input  wire [3:0] a, // Better to be explicit about the types even if 
                       // its not strictly necessary                            
  output reg  [3:0] b, // As mentioned in the comments, the error youre
                       // seeing is because b is a net type by default; when 
                       // describing logic in any always block, you need to 
                       // use variable types, like reg or logic (for 
                       // SystemVerilog); see the comment for a thread 
                       // describing the difference     
  input wire [5:0] c);                             
  
  // You dont really need any local signals as the logic is pretty simple                       
  
  always @(*) begin // Always use either always @(*), assign or 
                    // always_comb (if using SystemVerilog) for combinational logic                                                                 
    if (c == 6'b111111)   
      b = a; // For combinational logic, use blocking assignment ("=") 
             // instead of non-blocking assignment ("<="), NBA is used for 
             // registers/sequential logic                              
    else                                     
      b = 4'b0101;                            
  end                                                          
endmodule