'event' 是如何工作的？

Question

我正在学习 SystemVerilog event data types。但我无法理解仿真结果。

事件在 SystemVerilog 中如何工作？

更新

1 module events();
  2 // Declare a new event called ack
  3 event ack; 
  4 // Declare done as alias to ack 
  5 event done = ack; 
  6 // Event variable with no synchronization object
  7 event empty = null; 



  9 initial begin
 10    #1  -> ack;
 11    #1  -> empty;
 12    #1  -> done;
 13    #1  $finish;
 14 end
 15 
 16 always @ (ack)
 17 begin
 18   $display("ack event emitted");
 19 end
 20 
 21 always @ (done)
 22 begin
 23   $display("done event emitted");
 24 end
 25 
 26 /*
 27 always @ (empty)
 28 begin
 29   $display("empty event emitted");
 30 end
 31 */
 32 
 33 endmodule

如何显示如下？

 ack event emitted
 done event emitted
ack event emitted <== I don't understand here Why does it happens?
 done event emitted

我觉得应该是这样的

 ack event emitted

 done event emitted

 done event emitted

Answer 1

我想你可能对为什么多次打印事件感到困惑？看看第 5 行：

event done = ack;

现在 ack 和 done 是彼此的同义词，只要一个事件被触发，另一个事件也会被触发，因为每个事件都会在您获得 4 个打印输出时触发。

'event' 是如何工作的？

How does 'event' works?

system-verilog

更新